How can I simulate this vhdl using modelsim?

Question

I'm new to model sim. I have this vhdl

-- Code your design here

library IEEE;
use IEEE.std_logic_1164.all;
entity my_and is
port(x : in std_logic; y : in std_logic; z : out std_logic);
end entity my_and;
architecture rtl of my_and is
begin
 z <= x and y;
end architecture rtl;

And this test bench

library IEEE;
use IEEE.std_logic_1164.all;
entity my_tb is
end entity my_tb;
architecture rtl of my_tb is
 component my_and is
 port(x : in std_logic; y : in std_logic; z : out std_logic);
 end component my_and;
 signal clk : std_logic := '0';
 signal x : std_logic;
 signal y : std_logic;
 signal z : std_logic;
 constant period : time := 1 ns;
begin
 unit : my_and
 port map(x => x, y => y, z => z);
 clk_process : process
 begin
 clk <= '1';
 wait for period/2;
 clk <= '0';
 wait for period/2;
 end process clk_process;
 unit_proc : process(clk)
 variable count : integer := 0;
 begin
 if(clk'event and clk = '1') then
 if(count mod 4 = 0) then
 x <= '0';
 y <= '0';
 elsif(count mod 4 = 1) then
 x <= '1';
 y <= '0';
 elsif(count mod 4 = 2) then
 x <= '0';
 y <= '1';
 else
 x <= '1';
 y <= '1';
 end if;
 end if;
 count := count + 1;
 end process unit_proc;
end architecture rtl;

I've written the test bench by my self, I haven't used the tool. However when I do "Simulation -> Run simulation" the console tell me

Error loading design

I've set the test bench as top entity. Is there something I could check in order to run the simulation?

In terms of what the console spit out, here's what I get:

Compile of my_and.vhd was successful.
# Compile of my_and_tb.vhd was successful.
# 2 compiles, 0 failed with no errors.
vsim -gui work.my_and(rtl)
# vsim 
# Start time: 11:30:05 on Jul 28,2016
# Error loading design

• scary_jeff: There should have been more errors before the Error loading design. Have a look in the log and messages windows.
• user8352: The architecture name in end architecture arch; doesn't match the declared architecture name (rtl). Process unit_proc is missing a sensitivity list (clk). There's nothing that increments count. And there's nothing that sets the simulation duration (other than the implementation, e.g. run 10 ns). And count mod 2 = 2 is never true. Which also points out you should simply use values of count. Or you could use mod 4. You should insure count doesn't overflow. After fixing all that I get waveforms. Check those errors like scary_jeff suggests.
• user8469759: I fixed all you said, sorry for the silly mistakes. Still doesn't work.
• user16324: Looks like you're trying to simulate the gate,my_and not the testbench my_tb..
• user8469759: Shouldn't my "my_tb.." be the top entity?

Answer 1

If you have the student edition, make sure you have the license, and if you have the license, make sure youve copied it to the right folder