How to generate .xst file from command line + Xilinx-ISE

Question

I am trying to learn how to generate bit files from command line. Is there a way to generate the .xst script file from command line tools? I can only find mention of it being something that the GUI auto-generates.

To add some context, I build and generate a bit file for a simple design in the GUI then use the 'View Command Line Log' tool to generate the commands the tool used. Then use "Cleanup Project Files". I am just trying to execute the same commands manually from the command line. The first command is:

xst -ifn "C:/Users/Documents/XilinxProjects/SingleItemTest/item.xst" -ofn "C:/Users/Documents/XilinxProjects/SingleItemTest/item.syr" 

Which gives me:

ERROR:Xst:427 - Entry File C:/Users/Documents/XilinxProjects/SingleItemTest/item.xst not found

• user16324: Suggestion : auto-generate it, save it somewhere safe before Project Cleanup, then restore it before running XST from the command line.
• Nick: I'm attempting to develop a C++ application that automates the entire process beginning to end so finding a way to generate it outside of GUI would be preferable.
• user16324: The idea is to generate one, and use it as a template (edited if necessary) for future runs.

Answer 1

Our PoC-Library can run Xilinx XST from command line via Python3. We are using template files for XST, because each target device can have other XST options.

Here is a *.xst file for a 7-Series XST run:

set -xsthdpdir "xst"
run
-ifn {prjFile}
-use_new_parser {UseNewParser}
-ifmt {InputFormat}
-ofn {OutputName}
-ofmt {OutputFormat}
-p {Part}
-top {TopModuleName}
-opt_mode {OptimizationMode}
-opt_level {OptimizationLevel}
-power {PowerReduction}
-iuc {IgnoreSynthesisConstraintsFile}
-uc {SynthesisConstraintsFile}
-keep_hierarchy {KeepHierarchy}
-netlist_hierarchy {NetListHierarchy}
-rtlview {GenerateRTLView}
-glob_opt {GlobalOptimization}
-read_cores {ReadCores}
-sd {SearchDirectories}
-write_timing_constraints {WriteTimingConstraints}
-cross_clock_analysis {CrossClockAnalysis}
-hierarchy_separator {HierarchySeparator}
-bus_delimiter {BusDelimiter}
-case {Case}
-slice_utilization_ratio {SliceUtilizationRatio}
-bram_utilization_ratio {BRAMUtilizationRatio}
-dsp_utilization_ratio {DSPUtilizationRatio}
-lc {LUTCombining}
-reduce_control_sets {ReduceControlSets}
-fsm_extract {FSMExtract}
-fsm_encoding {FSMEncoding}
-safe_implementation {FSMSafeImplementation}
-fsm_style {FSMStyle}
-ram_extract {RAMExtract}
-ram_style {RAMStyle}
-rom_extract {ROMExtract}
-shreg_extract {ShRegExtract}
-rom_style {ROMStyle}
-auto_bram_packing {AutoBRAMPacking}
-resource_sharing {ResourceSharing}
-async_to_sync {ASyncToSync}
-use_dsp48 {UseDSP48}
-iobuf {IOBuf}
-max_fanout {MaxFanOut}
-bufg {BufG}
-register_duplication {RegisterDuplication}
-register_balancing {RegisterBalancing}
-optimize_primitives {OptimizePrimitives}
-use_clock_enable {UseClockEnable}
-use_sync_set {UseSyncSet}
-use_sync_reset {UseSyncReset}
-iob {PackIORegistersIntoIOBs}
-equivalent_register_removal {EquivalentRegisterRemoval}
-slice_utilization_ratio_maxmargin {SliceUtilizationRatioMaxMargin}

Source: https://github.com/VLSI-EDA/PoC/tree/master/xst