How to specify a minimum clock to output time in output timing constrain?

Question

In design, an external clock pin triggers a flip-flop, where the output goes to an external data pin.

Using Xilinx ISE, how can I specify a timing constraint, so the output should be held for some short time after the rising edge of the external clock?

I have looked in the Xilinx Constraints Guide, and it has:

OFFSET = OUT {time_after} AFTER {clock};

But this constraint allows output data to change immediately after the clock, thus with a minimum clock to output time of 0 ps, thereby specifying a duration of {time_after} where the output is undefined.

In compare, for inputs, the constrains is:

OFFSET = IN {time_before} VALID {time_valid} BEFORE {clock};

So here the duration of the defined data can be specified to {time_valid}, but with an independent start time given as {time_before}.

However, it appears that output timing constraints does not have the same flexibility, or I have not found it ☺

• Dave Tweed: You don't generally have explicit control over minimum output delays. If you're driving a device that has a minimum input hold time, you need to find a different way to guarantee it.
• EquipDev: If so, it sounds like a missing constrains possibility, since there will generally be some minimum output delay due to propagation delay from external clock pin, through flip-flop, and data back to external data pin. Is it possible to define a virtual clock based on a delay, and then constrain the external data to this?
• Dave Tweed: No, you can't have a "virtual clock", but you can have real clocks with delays. Read up on the features of DCMs and also the SelectIO capabilities. Xilinx gives you a lot of ways to control I/O, but it takes some effort to figure it all out.
• EquipDev: Thanks, creating an internal clock with a DCM may reduce the window, since the insertion delay of the clock will be removed, but the DCM will also add some clock uncertainty. Still odd that the Xilinx ISE constrain can't benefit from the fact that there is some minimum amount of clock to output delay.
• Dave Tweed: No, not odd at all. Yes, there may be some minimum delay, but the manufacturer cannot guarantee any particular value, so there's no point in having such a constraint in the tools.

Answer 1

The set_output_delay -min SDC syntax does this (Vivado XDC file.) You specify the 'min' value as a negative number as this event happens after the clock.

(What's SDC? Stands for Synopsys Design Constraints, which Xilinx, Altera and others have adopted for specifying timing and other routing / synthesis constraints. With Vivado, SDC replaces the old Xilinx ISE way of doing this. SDC is based on tcl language syntax.)

Generally,

• Use an ODDR (Xilinx) clock forwarding scheme to create your external clock. This gives the best control over clock skew, and will give you some hold time by design.
• Define this external forwarded clock as a virtual clock using create_generated_clock
• constrain your output to the virtual clock using set_output_delay.

More about this here: http://billauer.co.il/blog/2017/04/io-timing-constraints-meaning/

And... here: https://forums.xilinx.com/t5/Timing-Analysis/How-to-set-input-delay-and-output-delay-when-source-Synchronous/m-p/940275#M16092

(On Xilinx boards I'm vortex1601. When it comes to timing questions though, Avrum is da man ;-)

Maybe time to migrate to Vivado?