VHDL: Is it possible to have a "variable length" string in VHDL like in programming languages?

Question

According to the package named Standard in VHDL, the string is actually declared as array of character type where the character type itself is also defined within the package.

Provided that I am filling in a string with data which shall then be written to a file and the size of the string cannot be known in advance, how do I declare a "variable length string"?

I am aware that the Line type exists from textio. However, I don't know if it is possible to actually concatenate different line variables and then write them to a file. If this is possible then my problem can be solved.

• user16145658: I am aware that the Line type exists from textio. However, I don't know if it is possible to actually concatenate different line variables and then write them to a file. The string value of a Line can be evaluated with the suffix.all, e.g. for linebuff declared as and access type Line that would be linebuff.all. See (-2008) 8.3 Selected names "For a selected name that is used to denote the object designated by an access value, the suffix shall be the reserved word all. The prefix shall belong to an access type." You'd use a write [LINE, STRING] procedure to write concatenated strings.

Answer 1

A string is an array of characters with a fixed range. As for any other array type in VHDL, strings can be concatenated using the & operator resulting in a new string (with a new size).
For variable length strings you could use an access string type which can point to a variable length string. Similar questions were asked before.
If you need to handle arrays of strings, the easiest way is probably to define an array of fixed size strings along with a couple of trim() and pad() functions.

• quantum231: If I am to concatenate a string e.g str_a = str_a & temp_str, I am sure that will not work since str_a has a fixed size to begin with right? Anyway, I have worked out a solution using the line variable which you have mentioned.
• Paebbels: Using NUL as a fill character is not supported by all VHDL tools. Using characters greater then CHARACTER'val(127) in source code is not allowed (VHDL files are ASCII encoded not ANSI) and explicitly using CHARACTER'val(255) causes some VHDL tools to crash or to write the synthesis log window in reverse order .... Have a look at our PoC.strings package on how to implement several string functions for fixed sized strings.
• Jim Lewis: The CWRU packages implement a C like capability for VHDL strings. See bear.ces.case.edu/VHDL/index.html