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I am new to Cadence Allegro HDL for schematic design and for my first design i got this error. In 728 page document provided by cadence its is mention as follows, "Open the symbol for the component in Concept HDL or Part Developer and delete the port on the symbol, if it is not required. Then save the symbol. This will bring your symbol and entity ports in sync."

but I am not understanding what to do,please help.

asked Feb 1, 2016 at 9:52
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Use of the words "Port" and "Entity" suggests that you are working in the VHDL language, perhaps your schematic editor is a tool that allows the visual creation of VHDL designs.

The actual meaning of the message is clear : you are trying to connect a signal to a pin that doesn't exist. For example, take this AND gate

entity AND2 is
 port (A,B : in std_logic;
 O : out std_logic);
end entity;

If you try connecting 3 inputs (A,B,C) and one output to it, this will fail with a similar error message about port C.

Now the specific cause in your environment is not so clear to anyone who doesn't use that environment.

It might be that you have created a schematic symbol for a 3-input AND gate

schematic

simulate this circuit – Schematic created using CircuitLab

and as part of that symbol, associated it with a VHDL entity called "AND2" which of course represents a 2-input AND gate.

Now either you need to find the correct VHDL entity (presumably called "AND3") or delete the extra input pin (and make sure the other two are labelled "A" and "B").

But you must end up with a schematic symbol and a VHDL entity that match. i.e. both the graphic view and the VHDL textual view must describe teh same thing.

If you don't know how to do that, you need to find and study tutorial material for the specific tools you are using.

answered Feb 1, 2016 at 14:06
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  • \$\begingroup\$ thanks Brian,now all working fine .. actually i have updated the entity file and works fine.You also saying the same what I did yesterday.Thanks! \$\endgroup\$ Commented Feb 2, 2016 at 12:05
  • \$\begingroup\$ Can I just delete the entity folder in the symbol, if I am not using the VHDL stuff? \$\endgroup\$ Commented May 10, 2016 at 16:52

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