How to define a false path using design entities

Question

I'm trying to do a timing analysis on a design I wrote in VHDL. The design looks like this: enter image description here And the mux's are only activated in a way that the path is either:

in -> circuit1 -> circuit2 -> out

in -> circuit2 -> circuit3 -> out

Is there a way to 'tell' this to vivado so that the timing and implementation will take this in to account when determining if I meet the timing constraints?

I assume this will be done by 'setting false path'. But I'm not sure how exactly choose 'trough' what this path goes, since after synthethisation vivado 'joins' these entities (I'm using the 'rebuilt' setting during synthesis).

I have the circuits in separate entities, so I'm wondering if there is a way to use the 'set false path -trough' constraint with vhdl design entities.

Kind regards,

Michael

• Paebbels: Don't over constrain your design. I recommend to add these false path rules only if your design does not meet timings. Have you looked into UG900 - the Vivado Timing Guide? I think there was an mux example like your's.

Answer 1

If the mux control terms are common, I would expect the synthesis tool to only analyse active paths. You should check this first (look at the timing report and see what the critical path is).

You might be able to re-order your logic so the problem doesn't exist. I wonder if this might make optimisations simpler too (maybe).

If you really need to, its possible to false-path, from in to out, and set_min_delay from in to y, and x to out. False path is really never the best answer though, you'll never know you did it right (and you'll know if you did it wrong).