SASSembler

Resources

SIMD

• Vectorised character classification by James Faure on YouTube
• Eine Kleine Vectorized Classification
• Accelerated Zig Parser
• AVX2 what is the most efficient way to pack left based on a mask?
• SIMDized check which bytes are in a set by Wojciech Muła, GitHub
• Wojciech Muła's posts
• TODO: Some are referenced in source code but not here.

SASS

• TODO: Some of these have a related paper

• TODO: https://arxiv.org/abs/2503.20481 and https://arxiv.org/abs/2604.26889

• TODO: http://www.beyondgpu.com/NVIDIA-Microarchitecture-Sources/

• MaxAs, an SASS assembler for NVIDIA Maxwell and Pascal GPUs. By Scott Gray., GitHub wiki, explanation

• TuringAs, an SASS assembler for NVIDIA Volta and Turing GPUs. By Da Yan.

• AsFermi, an SASS assembler for NVIDIA Fermi GPUs. By Hou Yunqing.

• KeplerAs, an SASS assembler for NVIDIA Kepler GPUs. By Xiuxia Zhang.

• CuAssembler by cloudcores

• GAS by Da Yan.

• NVIDIA SASS disassembler and other tooling, related blog

• DocumentSASS: Unofficial description of the CUDA assembly (SASS) instruction sets.

• Nvidia Instruction Set Specification Generator by Kuter Dinel., SM90a (Hopper), SM89 (RTX4090), SM86

• Reversing Nvidia GPU’s SASS code

• SASS King by Florian Mattana., related blog

• crucible-notes by Grigory Evko (AI slop, often wrong!), GitHub pages

Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking

Links

• arXiv

Abstract

Every year, novel NVIDIA GPU designs are introduced. This rapid architectural and technological progression, coupled with a reluctance by manufacturers to disclose low-level details, makes it difficult for even the most proficient GPU software designers to remain up-to-date with the technological advances at a microarchitectural level. To address this dearth of public, microarchitectural-level information on the novel NVIDIA GPUs, independent researchers have resorted to microbenchmarks-based dissection and discovery. This has led to a prolific line of publications that shed light on instruction encoding, and memory hierarchy's geometry and features at each level. Namely, research that describes the performance and behavior of the Kepler, Maxwell and Pascal architectures. In this technical report, we continue this line of research by presenting the microarchitectural details of the NVIDIA Volta architecture, discovered through microbenchmarks and instruction set disassembly. Additionally, we compare quantitatively our Volta findings against its predecessors, Kepler, Maxwell and Pascal.

BibTeX

@misc{jia2018dissectingnvidiavoltagpu,
 title={Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking}, 
 author={Zhe Jia and Marco Maggioni and Benjamin Staiger and Daniele P. Scarpazza},
 year={2018},
 eprint={1804.06826},
 archivePrefix={arXiv},
 primaryClass={cs.DC},
 url={https://arxiv.org/abs/1804.06826}, 
}

Decoding CUDA Binary

Links

• IEEE Xplore
• Open PDF
• Related repo
• Related code (same stuff as repo w/ benchmarks)
• Special Registers Open PDF
• Decoded Instructions Open PDF
• Opcodes Open PDF
• File Format Open PDF

Abstract

NVIDIA’s software does not offer translation of assembly code to binary for their GPUs, since the specifications are closed-source. This work fills that gap. We develop a systematic method of decoding the Instruction Set Architectures (ISAs) of NVIDIA’s GPUs, and generating assemblers for different generations of GPUs. Our framework enables cross-architecture binary analysis and transformation. Making the ISA accessible in this manner opens up a world of opportunities for developers and researchers, enabling numerous optimizations and explorations that are unachievable at the source-code level. Our infrastructure has already benefited and been adopted in important applications including performance tuning, binary instrumentation, resource allocation, and memory protection.

BibTeX Citation

@INPROCEEDINGS{8661186,
 author={Hayes, Ari B. and Hua, Fei and Huang, Jin and Chen, Yanhao and Zhang, Eddy Z.},
 booktitle={2019 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)}, 
 title={Decoding CUDA Binary}, 
 year={2019},
 volume={},
 number={},
 pages={229-241},
 keywords={Instruction sets;Graphics processing units;Computer architecture;Registers;Decoding;Hardware;Encoding;CUDA;GPU;Code Generation;Code Translation and Transformation;Instruction Set Architecture (ISA)},
 doi={10.1109/CGO.2019.8661186}}