RedCuttle - Hardware In The Loop Testbench

Welcome to RedCuttle.

This project is the hardware and software for a JTAG/SWD/UART port multiplexer and switcher.

This hardware allows the control of multiple debuggers and targets to be connected to one another for development and testing purposes. The original motivation for this is the Hardware In The Loop testing of the Black Magic Debug firmware on Black Magic Probe hardware.

Controller

The debug/controller board provides the interface between a host PC over USB, and the carriers and targets connected to the backplane.

The controller features an STM32 MCU that handles the interface between the computer and the CAN bus that communicates with the carriers over the backplane.

Current plans are to use the UVCAN standard for the CAN connection, specified here.

External CAN connections use a 4-pin JST-GH:

1. Bus power (5V nominal)
2. CAN high
3. CAN low
4. Ground

These connectors are described here.

Backplane

The backplane manages the bus that routes the connected carriers together.

An example backplane

It has a CAN bus that ties all the carriers together, and exposes them to a debugging controller that then links the entire backplane to the computer managing the targets.

• 4HP (0.8" / 20.32mm) between carrier slots
  • Anything lower and there isn't sufficiant room for some targets.
• 3U height (5.25" / 133mm)
• M2.5 ground-plated mounting holes
• Designed to be chainable next to each-other in a larger rack.

Carrier

The carrier boards slot into a backplane and contain slots for several targets. The carriers interface over the backplane with the controller to connect the targets to the bus. Each carrier has an STM32 that communicates over CANBUS to the debugging to select which target is enabled and powerd.

Example of a PCIe-based carrier board

The interface from the carriers to the targets is described in the Connector section of the Target section.

The backplane slots for carriers are 4HP (0.8" or 20.32 mm) spaced, with the PCIe connector falling within the first HP of each slot, aligned with the card slide - about 0.73mm or 0.0287" to the right from the HP's center.

Carrier Connector x1

The carrier interfaces with the backplane through a PCIe x1 socket. Best effort is made to keep the pinout backwards-compatible with older hardware.

Even if the size of the PCIe connector is expanded in the future, it will still be backwards-compatible following this pinout.

Suggested parts:

• Lian Xin Technology XDMP-052-0360
  • PCIe x1 - 36 positions
  • Surface Mount

Carrier Connector Changelog

• 19/06/2026 - Documented reference connector layout designed by @zyp.

Targets

Each hardware target to test against is implemented as 42x38mm board (including edge connector) with an M.2 B-key card edge.

An example M.2 target board

GPIO

While the GPIO connections for targets can vary a bit depending on the requirements for a particular target, following this peripheral mapping will allow interfacing with the standard pinout on things like the breakout boards:

STM32

Genrally, LQFP STM32 targets follow the same pin to peripheral mappings. When possible, place pin 1 facing the top left corner of the board, and then you following GPIO can be cleanly routed straight up and over:

Routing example

Routing of STM32 targets

Identification

Each carrier has an I2C bus that gets connected to the target. Each target contains a small I2C EEPROM, typically a Microchip 24AA01 that is on a known bus address. This EEPROM contains identification and configuration information for the connected target in question.

The bus address used for targets is 1010000 or 0x50, from all address lines tied to ground.

Mechanical

Target boards are M.2 B-key cards, with a thickness of 0.8mm and edge contact beveling of 30-45 degrees. They are slightly shorter then the M.2_3042-xx-B specification at 41.3mm high (from bottom of card edge to top edge) instead of 42mm to allow clearance for fastening mounting two cards to the same mounting stud. The cards are also 38mm wide instead of 30mm to allow for more routing room for wider target MCUs. This makes the working area of the target board (excluding the M.2 card edge) 38x37.3mm.

The target boards are retained by an M3 bolt, going into a threaded SMD standoff, an Amphenol MDT420STD001. These can be retained using a matching Amphenol MDTSCW001 bolt. These M3 standoffs are more cost-effective then the typical M.2 standoffs, and are still used widely on motherboards.

While the M.2 spec calls for a 20 degree bevel with a 0.3mm edge clearance, PCB fabs are usually equipped for 30 or 45 degree bevels. Due to this being common, the majority of M.2 sockets will accept a 45 degree bevel with a 0.47mm edge clearance with no issues.

Note that JLCPCB will not bevel boards smaller them 50x50mm. To get around this, targets need to edge rail added along the top-side where the mounting hole is located, and panelized vertically.

Target Connector

The targets use custom-sized card sporting an M.2 B-key card-edge to connect to carriers. Best effort is made to keep the pinout backwards-compatible with older hardware.

Suggested connector parts:

• TE Connectivity 2199230-5 NGFF B-key
  • 4.2mm height
• JAE SM3ZS067U410AB
  • Original used by @zyp
  • 4.1mm

A shorter M.2 connector could be used, but I would stick with 4.2mm because it's fairly standardized, and gives enough clearance for SOIC components on the underside of the board if required.

M.2 B-key Pinout

Connector Changelog

• 19/06/2026 - Documented reference connector layout designed by @zyp.
• 28/06/2026 - Change pin 3 from MGMT_3V3 to constant +3V3 supply, add second +3V3 supply on pin 9. I2C EEPROM will always use 3.3v logic with STM32 controllers, so doesn't make sense to have a dedicated supply for it. A universal +3.3v supply is better suited, also making unused pin 9 a +3.3v supply as well for larger current capabilities.
• 29/06/2026 - Add dedicated RX/TX pins on 35/37 for debugger UART connection without sacrificing GPIO pins.
• 09/07/2026 - Add VGPIO on pin 58 so the target can inform the logic analyzer of the GPIO pin HIGH voltage.

Enclosures

SCHROFF RatiopacPRO

The backplanes fit nicely in Schroff RatiopacPRO cases, tested with the first iteration of the hardware designed by @zyp.

RatiopacPro case

A quarter rack (28HP) backplane fits nicely into the RatiopacPRO #24571-005, a 3U, 28HP, 315mm deep case.

SCHROFF Racks

The SCHROFF racks are easily adaptable to the backplane and cards. For racks, you want sizes that can be configured to at least 175mm long, which in the SCHROFF system allows for card depths of ~160mm + connector.

Theroretical shopping list for bare-bones 42HP half-rack:

• x2 Front Rails 34560-142
• x2 Back Rails 34560-642
• x4 Screw Inserts 34561-342
• x2 Side Panel 34560-185
• x1 Board Guides 24568-361

About CA200ドル in total.

License

The majority hardware and CAD components of this project are licensed under the CERN Open Hardware License v2.0. Check the LICENSE file closest to the hardware in question to see what license it is under.

Some hardware components, and the software components of this project are licensed under CC-BY-SA-4.0.

SPDX-License-Identifier: CERN-OHL-S-2.0 AND CC-BY-SA-4.0