This is a simple processor simulation for learning purposes
- Verilog 100%
| single_file | small changes | |
| alu.v | small changes | |
| control_unit.v | small changes | |
| instruction_mem.v | small changes | |
| processor.vcd | Small change | |
| processor_sim | Small change | |
| program_counter.v | small changes | |
| README.md | Update README.md | |
| register.v | small changes | |
| riscv_4bit_processor.v | small changes | |
| riscv_4bit_processor_tb.v | small changes | |
Simple 4-bit Processor
This is a simple 4 bit processor simulation for learning purposes, most parts of the codebase is self-explanatory :)
The HDL is compiled using icarus verilog iverilog compiler and simulation using gtkwave