Fix: Adjust DMI idle cycles for remote "Too soon" responses #2230

ALTracer commented 2026年04月14日 22:07:10 +02:00

Detailed description

• This is not a new feature.
• The existing problem is BMDA getting stuck in some busy-IO-loop in riscv_dmi_init() when operating a BMP with RISC-V acceleration enabled. BMP standalone not affected.
• This PR solves it by mirroring the logic to increment DMI idle cycles.

Tested on BMDA via blackpill-f411ce against modified Hazard3 v1.0.1 softcore on 1BitSquared Icebreaker v1.0e. I have added 10k pull-up options in PCF on JTAG pins, this improved the connection but the described bug didn't go away.
It should really be tested on other JTAG DTM RISC-V targets (like GD32VF103); e.g. RP2350 has a custom ADI DTM and will not be affected.
I can't say whether DTMCS Idle hint of 4 is correct https://github.com/Wren6991/Hazard3/blob/v1.0.1/hdl/debug/dtm/hazard3_jtag_dtm_core.v , the debugger is probably supposed to make do anyways.

Your checklist for this pull request

• I've read the Code of Conduct
• I've read the guidelines for contributing to this repository
• It builds for hardware native (see Building the firmware)
• It builds as BMDA (see Building the BMDA)
• I've tested it to the best of my ability
• My commit messages provide a useful short description of what the commits do

Closing issues

## Detailed description * This is not a new feature. * The existing problem is BMDA getting stuck in some busy-IO-loop in `riscv_dmi_init()` when operating a BMP with RISC-V acceleration enabled. BMP standalone not affected. * This PR solves it by mirroring the logic to increment DMI idle cycles. Tested on BMDA via `blackpill-f411ce` against modified Hazard3 v1.0.1 softcore on 1BitSquared Icebreaker v1.0e. I have added 10k pull-up options in PCF on JTAG pins, this improved the connection but the described bug didn't go away. It should really be tested on other JTAG DTM RISC-V targets (like GD32VF103); e.g. RP2350 has a custom ADI DTM and will not be affected. I can't say whether DTMCS Idle hint of 4 is correct https://github.com/Wren6991/Hazard3/blob/v1.0.1/hdl/debug/dtm/hazard3_jtag_dtm_core.v , the debugger is probably supposed to make do anyways. ## Your checklist for this pull request * [x] I've read the [Code of Conduct](https://codeberg.org/blackmagic-debug/blackmagic/src/CODE_OF_CONDUCT.md) * [x] I've read the [guidelines for contributing](https://codeberg.org/blackmagic-debug/blackmagic/src/CONTRIBUTING.md) to this repository * [x] It builds for hardware native (see [Building the firmware](https://codeberg.org/blackmagic-debug/blackmagic?tab=readme-ov-file#building-the-firmware)) * [x] It builds as BMDA (see [Building the BMDA](https://codeberg.org/blackmagic-debug/blackmagic?tab=readme-ov-file#building-black-magic-debug-app)) * [ ] I've tested it to the best of my ability * [x] My commit messages provide a useful short description of what the commits do ## Closing issues

ALTracer commented 2026年04月14日 22:09:43 +02:00

Snippet of BMDA bad log

ID code 0xdeadbeef: Hazard3 RISC-V DTM.
Enumerated 1 devices
0: IR length = 5, ID deadbeef
-> IR prescan: 0, postscan: 0
-> DR prescan: 0, postscan: 0
!JT043#
 K0
!JD0510#
 K1F
!JT021#
 K0
!JT031#
 K0
!JD200#
 K4071
!JT021#
 K0
RISC-V debug v0.13/v1.0 DMI
!JT043#
 K0
!JD0511#
 K10
!JT021#
 K0
!RSJ#
 K0
!Rd00040700000011#
 E303
!Rd00040700000011#
 E303
!Rd00040700000011#
 E303
!Rd00040700000011#
 E303
!Rd00040700000011#

Snippet of BMDA good log after this fix

RISC-V debug v0.13/v1.0 DMI
!JT043#
 K0
!JD0511#
 K10
!JT021#
 K0
!RSJ#
 K0
!Rd00040700000011#
 E303
!Rd00050700000011#
 E303
!Rd00060700000011#
 KA20C4300
remote_v4_riscv_jtag_dmi_read: 00000011 -> 00430ca2
riscv_dmi_read: 00000011 -> 00430ca2
RISC-V debug v0.13 DM
riscv_dmi_write: 00000010 <- 00000001
!RD0006070000001000000001#
 K0
remote_v4_riscv_jtag_dmi_write: 00000010 <- 00000001
riscv_dmi_write: 00000010 <- 03ffffc1
!RD0006070000001003ffffc1#
 K0
remote_v4_riscv_jtag_dmi_write: 00000010 <- 03ffffc1
!Rd00060700000010#
 K01000000
remote_v4_riscv_jtag_dmi_read: 00000010 -> 00000001
riscv_dmi_read: 00000010 -> 00000001
riscv_dmi_write: 00000010 <- 00000001
!RD0006070000001000000001#
 K0
remote_v4_riscv_jtag_dmi_write: 00000010 <- 00000001
!Rd00060700000011#
 KA20C4300
remote_v4_riscv_jtag_dmi_read: 00000011 -> 00430ca2
riscv_dmi_read: 00000011 -> 00430ca2
riscv_dmi_write: 00000010 <- 80000001
!RD0006070000001080000001#
 K0
remote_v4_riscv_jtag_dmi_write: 00000010 <- 80000001
!Rd00060700000011#
 KA2034300
remote_v4_riscv_jtag_dmi_read: 00000011 -> 004303a2
riscv_dmi_read: 00000011 -> 004303a2
riscv_dmi_write: 00000010 <- 00000001
!RD0006070000001000000001#
 K0
remote_v4_riscv_jtag_dmi_write: 00000010 <- 00000001
!Rd00060700000016#
 K01000002
remote_v4_riscv_jtag_dmi_read: 00000016 -> 02000001
riscv_dmi_read: 00000016 -> 02000001
Hart has 1 data registers and 2 progbuf registers
Attempting 32-bit read on misa
Reading 32-bit CSR 301

<details> <summary>Snippet of BMDA bad log</summary> ``` ID code 0xdeadbeef: Hazard3 RISC-V DTM. Enumerated 1 devices 0: IR length = 5, ID deadbeef -> IR prescan: 0, postscan: 0 -> DR prescan: 0, postscan: 0 !JT043# K0 !JD0510# K1F !JT021# K0 !JT031# K0 !JD200# K4071 !JT021# K0 RISC-V debug v0.13/v1.0 DMI !JT043# K0 !JD0511# K10 !JT021# K0 !RSJ# K0 !Rd00040700000011# E303 !Rd00040700000011# E303 !Rd00040700000011# E303 !Rd00040700000011# E303 !Rd00040700000011# ``` </details> <details> <summary>Snippet of BMDA good log after this fix</summary> ``` RISC-V debug v0.13/v1.0 DMI !JT043# K0 !JD0511# K10 !JT021# K0 !RSJ# K0 !Rd00040700000011# E303 !Rd00050700000011# E303 !Rd00060700000011# KA20C4300 remote_v4_riscv_jtag_dmi_read: 00000011 -> 00430ca2 riscv_dmi_read: 00000011 -> 00430ca2 RISC-V debug v0.13 DM riscv_dmi_write: 00000010 <- 00000001 !RD0006070000001000000001# K0 remote_v4_riscv_jtag_dmi_write: 00000010 <- 00000001 riscv_dmi_write: 00000010 <- 03ffffc1 !RD0006070000001003ffffc1# K0 remote_v4_riscv_jtag_dmi_write: 00000010 <- 03ffffc1 !Rd00060700000010# K01000000 remote_v4_riscv_jtag_dmi_read: 00000010 -> 00000001 riscv_dmi_read: 00000010 -> 00000001 riscv_dmi_write: 00000010 <- 00000001 !RD0006070000001000000001# K0 remote_v4_riscv_jtag_dmi_write: 00000010 <- 00000001 !Rd00060700000011# KA20C4300 remote_v4_riscv_jtag_dmi_read: 00000011 -> 00430ca2 riscv_dmi_read: 00000011 -> 00430ca2 riscv_dmi_write: 00000010 <- 80000001 !RD0006070000001080000001# K0 remote_v4_riscv_jtag_dmi_write: 00000010 <- 80000001 !Rd00060700000011# KA2034300 remote_v4_riscv_jtag_dmi_read: 00000011 -> 004303a2 riscv_dmi_read: 00000011 -> 004303a2 riscv_dmi_write: 00000010 <- 00000001 !RD0006070000001000000001# K0 remote_v4_riscv_jtag_dmi_write: 00000010 <- 00000001 !Rd00060700000016# K01000002 remote_v4_riscv_jtag_dmi_read: 00000016 -> 02000001 riscv_dmi_read: 00000016 -> 02000001 Hart has 1 data registers and 2 progbuf registers Attempting 32-bit read on misa Reading 32-bit CSR 301 ``` </details>