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Fix: add a remap for three RISC-V FPU CSR for GDB #2224

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dragonmux merged 2 commits from ALTracer/blackmagic:fix/rv32-fpu-csr into main 2026年04月04日 12:40:07 +02:00
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Detailed description

  • This is a small fix/follow-up to #1766.
  • The existing problem is GDB p-packet (read single register) for CSR fflags, frm, fcsr (66, 67, 68) ending up remapped wrong for riscv_csr_read() layer. In particular, this was reported to generate errors in VSCode debug.
  • This PR solves it by adding a couple if-branches to remap the three FPU CSRs appropriately.

Not tested, a RISC-V processor with F-extension is required.
There was a technically unhandled range from 66 up to 128 that used to get remapped to 0x1020 like this, I'm not sure if it should be blocked, or whether it's already unreachable thanks to riscv_build_target_description().
Should the debugger (BMD) enable the FPU when it's present but disabled (default from power-up) by user to conserve power etc.? Then such reads shouldn't ever fail...

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## Detailed description * This is a small fix/follow-up to #1766. * The existing problem is GDB p-packet (read single register) for CSR `fflags`, `frm`, `fcsr` (66, 67, 68) ending up remapped wrong for `riscv_csr_read()` layer. In particular, this was reported to generate errors in VSCode debug. * This PR solves it by adding a couple if-branches to remap the three FPU CSRs appropriately. Not tested, a RISC-V processor with F-extension is required. There was a technically unhandled range from 66 up to 128 that used to get remapped to 0x1020 like this, I'm not sure if it should be blocked, or whether it's already unreachable thanks to `riscv_build_target_description()`. Should the debugger (BMD) enable the FPU when it's present but disabled (default from power-up) by user to conserve power etc.? Then such reads shouldn't ever fail... ## Your checklist for this pull request * [x] I've read the [Code of Conduct](https://codeberg.org/blackmagic-debug/blackmagic/src/CODE_OF_CONDUCT.md) * [x] I've read the [guidelines for contributing](https://codeberg.org/blackmagic-debug/blackmagic/src/CONTRIBUTING.md) to this repository * [x] It builds for hardware native (see [Building the firmware](https://codeberg.org/blackmagic-debug/blackmagic?tab=readme-ov-file#building-the-firmware)) * [x] It builds as BMDA (see [Building the BMDA](https://codeberg.org/blackmagic-debug/blackmagic?tab=readme-ov-file#building-black-magic-debug-app)) * [ ] I've tested it to the best of my ability * [x] My commit messages provide a useful short description of what the commits do ## Closing issues
dragonmux requested changes 2026年04月04日 11:26:48 +02:00
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Only the one small thing and with that taken care of we're happy to merge this - it looks great. We understand that it's not been able to be tested, but it puts the CSR reads where they're meant to be per the spec, and so we have no doubt as to its functionality being okay and working well.

With regards force powering the FPU up - no, this is on the user to do if their firmware needs it.. because there are ABI things in play if that were done without the firmware knowing, and what we should really do is to guard FPU code paths on whether the unit is actually enabled instead. However, that is a pure improvement on the current code to make it behave more nicely, and not a fundamental fix like this - so should be a separate PR anyhow.

Only the one small thing and with that taken care of we're happy to merge this - it looks great. We understand that it's not been able to be tested, but it puts the CSR reads where they're meant to be per the spec, and so we have no doubt as to its functionality being okay and working well. With regards force powering the FPU up - no, this is on the user to do if their firmware needs it.. because there are ABI things in play if that were done without the firmware knowing, and what we should really do is to guard FPU code paths on whether the unit is actually enabled instead. However, that is a pure improvement on the current code to make it behave more nicely, and not a fundamental fix like this - so should be a separate PR anyhow.
@ -162,6 +162,10 @@ static size_t riscv32_reg_read(target_s *target, const uint32_t reg, void *data,
return riscv32_bool_to_4(riscv_csr_read(hart, RV_DPC, data));
if (reg >= RV_CSR_GDB_OFFSET)
return riscv32_bool_to_4(riscv_csr_read(hart, reg - RV_CSR_GDB_OFFSET, data));
if (reg >= RV_FPU_GDB_CSR_OFFSET + 3 && reg < RV_CSR_GDB_OFFSET)

The && stanza here is already given by the if above, meaning worse codegen for no gain if the compiler doesn't realise that - you can just drop the check for that it's less than RV_CSR_GDB_OFFSET as it has to be because of if ordering.

The `&&` stanza here is already given by the `if` above, meaning worse codegen for no gain if the compiler doesn't realise that - you can just drop the check for that it's less than RV_CSR_GDB_OFFSET as it has to be because of `if` ordering.
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Dropped the redundant check. Added commentary instead.

Dropped the redundant check. Added commentary instead.
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ALTracer force-pushed fix/rv32-fpu-csr from 52a5d55a80
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2026年04月04日 12:13:12 +02:00
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LGTM, merging. Thank you for the contribution!

LGTM, merging. Thank you for the contribution!
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