Feature: re-enable non-halting RTT on a few targets #2037

ALTracer commented 2024年12月30日 15:01:28 +01:00 (Migrated from github.com)

Detailed description

• This is not a new feature, this restores BMD behaviour before #1962.
• The existing problem is BMP with RTT halts all its targets by default to check controlblock contents in SRAM. This is incompatible with any real-time firmware, we get packet loss and CRC errors.
• The PR solves it by enabling the provisioned target flag on targets where I've tested RTT to return non-garbage data even if the processor keeps running.

Testcases are Arduino/stm32duino RTT_Stream speedtest.ino sketch and Eclipse uOS++ ilie with Segger's RTT sources from their examples zip. Unfortunately I haven't been able to find an independent opensource implementation of RTT to include in libopencm3-based firmware testcases, and I don't want to dip in Rust for this.
Confirmed to increase RTT data read speed on Nucleo-G071RB and GD32E508ZE, to stop dropping Rx SPI words on WeAct Studio AT32F403ACG.
Pending testing on STM32F103CB, GD32F103CB, GD32F303CC (all WeAct Studio BluePill-Plus boards).
BMP platform used is mostly blackpill-f411ce but stlink/swlink is also possible. BMDA is likewise affected.

Note I cannot test GD32F2 and GD32E230, where it is unknown to work. Especially so I cannot test on TM4C123 which is the one and only reported problematic Cortex-M4F core.

A good metric of detecting DUT halts without parsing SWD traffic or BMP advanced logging or running any realtime communication protocols (or wiggling GPIOs) is running a peripheral TIMer in Output PWM mode at 100% duty cycle with DBGMCU APB freeze bit set for it -- as soon as Processing Element gets halted, TIM_OCx goes low (confirmed on oscilloscope watching SWD), and goes back high on resuming, and there's no extra spurious transitions.

First commit (which touches target/cortexm.c) is obviously not intended to land on main as part of this PR, it is only provided for convenience of A/B-testing without reflashing BMPs (there's a runtime switch for monitor mem_nohalt enable)

If wildcard-enabling this behaviour on entire families not flavours is acceptable, then I can move the flag-setting code out of branches and simplify firmware further.

Your checklist for this pull request

• I've read the Code of Conduct
• I've read the guidelines for contributing to this repository
• It builds for hardware native (see Building the firmware)
• It builds as BMDA (see Building the BMDA)
• I've tested it to the best of my ability
• My commit messages provide a useful short description of what the commits do

Closing issues

## Detailed description * This is not a **new** feature, this restores BMD behaviour before #1962. * The existing problem is BMP with RTT halts all its targets by default to check controlblock contents in SRAM. This is incompatible with any real-time firmware, we get packet loss and CRC errors. * The PR solves it by enabling the provisioned target flag on targets where I've tested RTT to return non-garbage data even if the processor keeps running. Testcases are Arduino/stm32duino RTT_Stream speedtest.ino sketch and Eclipse uOS++ ilie with Segger's RTT sources from their examples zip. Unfortunately I haven't been able to find an independent opensource implementation of RTT to include in libopencm3-based firmware testcases, and I don't want to dip in Rust for this. Confirmed to increase RTT data read speed on Nucleo-G071RB and GD32E508ZE, to stop dropping Rx SPI words on WeAct Studio AT32F403ACG. Pending testing on STM32F103CB, GD32F103CB, GD32F303CC (all WeAct Studio BluePill-Plus boards). BMP platform used is mostly `blackpill-f411ce` but stlink/swlink is also possible. BMDA is likewise affected. Note I cannot test GD32F2 and GD32E230, where it is unknown to work. Especially so I cannot test on TM4C123 which is the one and only reported problematic Cortex-M4F core. A good metric of detecting DUT halts without parsing SWD traffic or BMP advanced logging or running any realtime communication protocols (or wiggling GPIOs) is running a peripheral TIMer in Output PWM mode at 100% duty cycle with DBGMCU APB freeze bit set for it -- as soon as Processing Element gets halted, TIM_OCx goes low (confirmed on oscilloscope watching SWD), and goes back high on resuming, and there's no extra spurious transitions. First commit (which touches target/cortexm.c) is obviously not intended to land on `main` as part of this PR, it is only provided for convenience of A/B-testing without reflashing BMPs (there's a runtime switch for `monitor mem_nohalt enable`) If wildcard-enabling this behaviour on entire families not flavours is acceptable, then I can move the flag-setting code out of branches and simplify firmware further. ## Your checklist for this pull request * [x] I've read the [Code of Conduct](https://github.com/blackmagic-debug/blackmagic/blob/main/CODE_OF_CONDUCT.md) * [x] I've read the [guidelines for contributing](https://github.com/blackmagic-debug/blackmagic/blob/main/CONTRIBUTING.md) to this repository * [x] It builds for hardware native (see [Building the firmware](https://github.com/blackmagic-debug/blackmagic?tab=readme-ov-file#building-black-magic-debug-firmware)) * [x] It builds as BMDA (see [Building the BMDA](https://github.com/blackmagic-debug/blackmagic?tab=readme-ov-file#building-black-magic-debug-app)) * [x] I've tested it to the best of my ability * [x] My commit messages provide a useful short description of what the commits do ## Closing issues

beefdeadbeef commented 2025年09月06日 14:16:08 +02:00 (Migrated from github.com)

FWIW i've tested this on AT32F42x (namely at32f425f8p7) and AT32F437 found on at-start-f437 eval board.
works for me.

FWIW i've tested this on AT32F42x (namely at32f425f8p7) and AT32F437 found on at-start-f437 eval board. works for me.

markrages commented 2025年12月17日 19:04:48 +01:00 (Migrated from github.com)

Please also add non-halting for nRF54L target.

Please also add non-halting for nRF54L target.

markrages commented 2025年12月17日 22:17:39 +01:00 (Migrated from github.com)

Thank you

Thank you

Copper280z commented 2025年12月20日 17:16:32 +01:00 (Migrated from github.com)

Tested non-halting access on an STM32H723 nucleo using BMDA+stlink and got good data via RTT.

Tested non-halting access on an STM32H723 nucleo using BMDA+stlink and got good data via RTT.

ALTracer commented 2026年03月27日 18:47:22 +01:00

@dragonmux wrote in #2037 (comment):

Please address the small number of review notes in cortexm.c and then we'll get this merged.

They are about first commit in cortexm.c adding a helper command to toggle whether RTT access functions halts the processor or not; I will drop this commit altogether, it was only a measure to accelerate retesting without recompiling and reflashing BMF. Configurables are against the idea of automatic Black Magic Debug, and RTT should Just Work for every Cortex-M SoC (that has been tested so far). If anyone needs it, I'll keep it as a text patch here.

From 1779ee5021e765cd4d0c59b0a780341109f4eca5 Mon Sep 17 00:00:00 2001
From: ALTracer <11005378+ALTracer@users.noreply.github.com>
Date: 2024年11月21日 13:16:56 +0300
Subject: [PATCH] cortexm: Allow toggling non-halting option via a runtime
 command
---
 src/target/cortexm.c | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)
diff --git a/src/target/cortexm.c b/src/target/cortexm.c
index ce59bf5c..90394069 100644
--- a/src/target/cortexm.c
+++ b/src/target/cortexm.c
@@ -51,9 +51,16 @@
 #define CORTEXM_MAX_REG_COUNT (CORTEXM_GENERAL_REG_COUNT + CORTEX_FLOAT_REG_COUNT + CORTEXM_TRUSTZONE_REG_COUNT)
 
 static bool cortexm_vector_catch(target_s *target, int argc, const char **argv);
+#ifdef ENABLE_RTT
+static bool cortexm_mem_nohalt(target_s *target, int argc, const char **argv);
+#include "rtt.h"
+#endif
 
 const command_s cortexm_cmd_list[] = {
 	{"vector_catch", cortexm_vector_catch, "Catch exception vectors"},
+#ifdef ENABLE_RTT
+	{"mem_nohalt", cortexm_mem_nohalt, "Toggle halting during memory accesses (affects RTT)"},
+#endif
 	{NULL, NULL, NULL},
 };
 
@@ -1290,6 +1297,31 @@ static bool cortexm_vector_catch(target_s *target, int argc, const char **argv)
 	return true;
 }
 
+#ifdef ENABLE_RTT
+static bool cortexm_mem_nohalt(target_s *target, int argc, const char **argv)
+{
+	bool enable = false;
+	if (argc > 2) {
+		tc_printf(target, "Usage: monitor mem_nohalt <enable|disable>");
+		return false;
+	}
+	if ((argc == 2) && parse_enable_or_disable(argv[1], &enable)) {
+		if (enable)
+			target->target_options |= TOPT_NON_HALTING_MEM_IO;
+		else
+			target->target_options &= ~TOPT_NON_HALTING_MEM_IO;
+		/* Force reapplying halt settings in rtt.c */
+		rtt_found = false;
+
+		return true;
+	}
+	tc_printf(target, "Target allows non-halting memory IO: %s\n",
+		target->target_options & TOPT_NON_HALTING_MEM_IO ? "yes" : "no");
+	return true;
+}
+
+#endif
+
 static bool cortexm_hostio_request(target_s *const target)
 {
 	/* Read out the information from the target needed to complete the request */
-- 
2.34.1

@dragonmux wrote in https://codeberg.org/blackmagic-debug/blackmagic/pulls/2037#issuecomment-12231498: > Please address the small number of review notes in cortexm.c and then we'll get this merged. They are about first commit in cortexm.c adding a helper command to toggle whether RTT access functions halts the processor or not; I will drop this commit altogether, it was only a measure to accelerate retesting without recompiling and reflashing BMF. Configurables are against the idea of automatic Black Magic Debug, and RTT should Just Work for every Cortex-M SoC (that has been tested so far). If anyone needs it, I'll keep it as a text patch here. ```diff From 1779ee5021e765cd4d0c59b0a780341109f4eca5 Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: 2024年11月21日 13:16:56 +0300 Subject: [PATCH] cortexm: Allow toggling non-halting option via a runtime command --- src/target/cortexm.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/src/target/cortexm.c b/src/target/cortexm.c index ce59bf5c..90394069 100644 --- a/src/target/cortexm.c +++ b/src/target/cortexm.c @@ -51,9 +51,16 @@ #define CORTEXM_MAX_REG_COUNT (CORTEXM_GENERAL_REG_COUNT + CORTEX_FLOAT_REG_COUNT + CORTEXM_TRUSTZONE_REG_COUNT) static bool cortexm_vector_catch(target_s *target, int argc, const char **argv); +#ifdef ENABLE_RTT +static bool cortexm_mem_nohalt(target_s *target, int argc, const char **argv); +#include "rtt.h" +#endif const command_s cortexm_cmd_list[] = { {"vector_catch", cortexm_vector_catch, "Catch exception vectors"}, +#ifdef ENABLE_RTT + {"mem_nohalt", cortexm_mem_nohalt, "Toggle halting during memory accesses (affects RTT)"}, +#endif {NULL, NULL, NULL}, }; @@ -1290,6 +1297,31 @@ static bool cortexm_vector_catch(target_s *target, int argc, const char **argv) return true; } +#ifdef ENABLE_RTT +static bool cortexm_mem_nohalt(target_s *target, int argc, const char **argv) +{ + bool enable = false; + if (argc > 2) { + tc_printf(target, "Usage: monitor mem_nohalt <enable|disable>"); + return false; + } + if ((argc == 2) && parse_enable_or_disable(argv[1], &enable)) { + if (enable) + target->target_options |= TOPT_NON_HALTING_MEM_IO; + else + target->target_options &= ~TOPT_NON_HALTING_MEM_IO; + /* Force reapplying halt settings in rtt.c */ + rtt_found = false; + + return true; + } + tc_printf(target, "Target allows non-halting memory IO: %s\n", + target->target_options & TOPT_NON_HALTING_MEM_IO ? "yes" : "no"); + return true; +} + +#endif + static bool cortexm_hostio_request(target_s *const target) { /* Read out the information from the target needed to complete the request */ -- 2.34.1 ```

dragonmux commented 2026年03月27日 23:19:46 +01:00

Okay, that works. We'll approve and merge this once the pipeline completes then as the rest all looked good

Okay, that works. We'll approve and merge this once the pipeline completes then as the rest all looked good