Detailed description
- This is a completely new feature.
- There are existing problems on multi-AP chips like STM32H7, H5, MP15 regarding miscellaneous Debug features setup, some of which has to go through APB-D AP and not MCU's MEM-AP (AHB-AP).
- This PR solves some of these problems by introducing runtime management and hooks for AXI-AP AP0 and APB-D AP1 of MP15.
This was written as a PoC in December, before the cortexar STC/LDC DTRRX speedups got developed and tested. Using AXI-AP may provide background access to entire DDR3 and SYSRAM without halting either CA7 of the platform (or single CA7 on MP151).
I need in particular the APB-D to be able to setup the CoreSight SWO block in SoC system scope, which is shared between CA7 MPCore and CM4 and hence neither of them can write to its configuration registers page. The rest (ITM, DWT, RCC) are accessible in some sort and can be poked via Orbuculum's gdbtrace.init script.
Your checklist for this pull request
- I've read the Code of Conduct
- I've read the guidelines for contributing to this repository
- It builds for hardware native (see Building the firmware)
- It builds as BMDA (see Building the BMDA)
- I've tested it to the best of my ability
- My commit messages provide a useful short description of what the commits do
Closing issues
## Detailed description
* This is a completely new feature.
* There are existing problems on multi-AP chips like STM32H7, H5, MP15 regarding miscellaneous Debug features setup, some of which has to go through APB-D AP and not MCU's MEM-AP (AHB-AP).
* This PR solves some of these problems by introducing runtime management and hooks for AXI-AP AP0 and APB-D AP1 of MP15.
This was written as a PoC in December, before the cortexar STC/LDC DTRRX speedups got developed and tested. Using AXI-AP may provide background access to entire DDR3 and SYSRAM without halting either CA7 of the platform (or single CA7 on MP151).
I need in particular the APB-D to be able to setup the CoreSight SWO block in SoC system scope, which is shared between CA7 MPCore and CM4 and hence neither of them can write to its configuration registers page. The rest (ITM, DWT, RCC) are accessible in some sort and can be poked via Orbuculum's gdbtrace.init script.
## Your checklist for this pull request
* [x] I've read the [Code of Conduct](https://github.com/blackmagic-debug/blackmagic/blob/main/CODE_OF_CONDUCT.md)
* [x] I've read the [guidelines for contributing](https://github.com/blackmagic-debug/blackmagic/blob/main/CONTRIBUTING.md) to this repository
* [x] It builds for hardware native (see [Building the firmware](https://github.com/blackmagic-debug/blackmagic?tab=readme-ov-file#building-black-magic-debug-firmware))
* [x] It builds as BMDA (see [Building the BMDA](https://github.com/blackmagic-debug/blackmagic?tab=readme-ov-file#building-black-magic-debug-app))
* [ ] I've tested it to the best of my ability
* [x] My commit messages provide a useful short description of what the commits do
## Closing issues