Az Delivery ESP32 DevKitC V2 PIN names/number

Question

i wonder where to find out the PIN names for the Az Delivery ESP32 DevKitC V2. There is a pin out graphic, but it does not say how the Pin addresses are: https://cdn.shopify.com/s/files/1/1509/1638/files/ESP_-_32_NodeMCU_Developmentboard_Pinout_Diagram.jpg?4479111012146266271

I thought maybe it's just the number of the GPIOs but that's wrong. In the first example script only PIN 1 was named as the address for the board intern LED.

• Majenko: There are no pin names on the ESP32. GIOx is pin x.
• Stack: Well there is a GIPIO 0 and 0 is already the board LED, so that's not possible
• Majenko: It's perfectly possible. Connections aren't exclusive. You can have a connection going to both a pin at the edge of the board and to an LED. Look at pin 13 of the Arduino - that goes to a pin on the edge of the board and to the on-board LED.

Answer 1

ESP32 boards don't use "names" for their IO pins. There is a direct 1:1 mapping between the internal "GPIO" number and the pin number.

To do something with pin G21 on the board you use pin number 21. To do something with pin G14 you use pin number 14.

By all accounts that board differs from other ESP32 devkits in that the LED is on GPIO1 rather than the normal GPIO0 that all the other boards use. I suspect that this is the source of your confusion.

• Stack: To finalize the confusion you need to digitalWrite(1,LOW) and not digitalWrite(1,HIGH) to turn the LED on. Ooof
• jsotola: @Stack one end of the LED is connected to V+ ... pulling the other end low lights it ... it is not so confusing really ... if it continues to give you problems, then define ON and OFF ... in the end, pulling a pin of a device low, to activate it, is very common practice ... just look at solenoid driver circuits
• Majenko: This "active low" driving method stems from the early days of semiconductors when you would have a low impedance LOW and a high impedance HIGH output - for example RTL where a transistor pulls the output down and a resistor pulls it up. Later when CMOS came on the scene you'd have a low resistance N-channel FET for the LOW and a higher resistance P-channel FET for the HIGH allowing more current to be sunk than could be sourced by an output. These days it's not a problem as the P- and N-channel FETs are much more closely matched - but the hangover is still there in many designers' minds.