Digital Logic Families Part-I

Digital Logic Families

Part-I

Jan-7-2025

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../images/main/bullet_green_ball.gif Digital Logic Families.

Logic families can be classified broadly according to the technologies they are built with. In earlier days we had vast number of these technologies, as you can see in the list below.

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DL : Diode Logic.
RTL : Resistor Transistor Logic.
DTL : Diode Transistor Logic.
HTL : High threshold Logic.
TTL : Transistor Transistor Logic.
I2L : Integrated Injection Logic.
ECL : Emitter coupled logic.
MOS : Metal Oxide Semiconductor Logic (PMOS and NMOS).
CMOS : Complementary Metal Oxide Semiconductor Logic.

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Among these, only CMOS is most widely used by the ASIC (Chip) designers; we will still try to understand a few of the extinct / less used technologies. More in-depth explanation of CMOS will be covered in the VLSI section.

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../images/main/bulllet_4dots_orange.gif Basic Concepts

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Before we start looking at the how gates are built using various technologies, we need to understand a few basic concepts. These concepts will go long way i.e. if you become a ASIC designer or Board designer, you may need to know these concepts very well.

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Fan-in.
Fan-out.
Noise Margin.
Power Dissipation.
Gate Delay.
Wire Delay.
Skew.
Voltage Threshold.

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../images/main/bullet_star_pink.gif Fan-in

Fan-in is the number of inputs a gate has, like a two input AND gate has fan-in of two, a three input NAND gate as a fan-in of three. So a NOT gate always has a fan-in of one. The figure below shows the effect of fan-in on the delay offered by a gate for a CMOS based gate. Normally delay increases following a quadratic function of fan-in.

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../images/digital/fanin_delay.gif

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../images/main/bullet_star_pink.gif Fan-out

The number of gates that each gate can drive, while providing voltage levels in the guaranteed range, is called the standard load or fan-out. The fan-out really depends on the amount of electric current a gate can source or sink while driving other gates. The effects of loading a logic gate output with more than its rated fan-out has the following effects.

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In the LOW state the output voltage VOL may increase above VOLmax.
In the HIGH state the output voltage VOH may decrease below VOHmin.
The operating temperature of the device may increase thereby reducing the reliability of the device and eventually causing the device failure.
Output rise and fall times may increase beyond specifications
The propagation delay may rise above the specified value.

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Normally as in the case of fan-in, the delay offered by a gate increases with the increase in fan-out.

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../images/digital/fanout_delay.gif

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../images/main/bullet_star_pink.gif Gate Delay

Gate delay is the delay offered by a gate for the signal appearing at its input, before it reaches the gate output. The figure below shows a NOT gate with a delay of "Delta", where output X' changes only after a delay of "Delta". Gate delay is also known as propagation delay.

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../images/digital/gate_delay.gif

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Gate delay is not the same for both transitions, i.e. gate delay will be different for low to high transition, compared to high to low transition.

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Low to high transition delay is called turn-on delay and High to low transition delay is called turn-off delay.

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../images/main/bullet_star_pink.gif Wire Delay

Gates are connected together with wires and these wires do delay the signal they carry, these delays become very significant when frequency increases, say when the transistor sizes are sub-micron. Sometimes wire delay is also called flight time (i.e. signal flight time from point A to B). Wire delay is also known as transport delay.

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../images/digital/wire_delay.gif

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../images/main/bullet_star_pink.gif Skew

The same signal arriving at different parts of the design with different phase is known as skew. Skew normally refers to clock signals. In the figure below, clock signal CLK reaches flip-flop FF0 at time t0, so with respect to the clock phase at the source, it has at FF0 input a clock skew of t0 time units. Normally this is expressed in nanoseconds.

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../images/digital/clock_skew.gif

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The waveform below shows how clock looks at different parts of the design. We will discuss the effects of clock skew later.

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../images/digital/clock_skew_wave.gif

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../images/main/bullet_star_pink.gif Logic levels

Logic levels are the voltage levels for logic high and logic low.

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VO_Hmin : The minimum output voltage in HIGH state (logic '1'). VO_Hmin is 2.4 V for TTL and 4.9 V for CMOS.
VO_Lmax : The maximum output voltage in LOW state (logic '0'). VO_Lmax is 0.4 V for TTL and 0.1 V for CMOS.
VI_Hmin : The minimum input voltage guaranteed to be recognised as logic 1. VI_Hmin is 2 V for TTL and 3.5 V for CMOS.
VI_Lmax : The maximum input voltage guaranteed to be recognised as logic 0. VI_Lmax is 0.8 V for TTL and 1.5 V for CMOS.

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../images/main/bullet_star_pink.gif Current levels

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IO_Hmin: The maximum current the output can source in HIGH state while still maintaining the output voltage above VO_Hmin.
IO_Lmax : The maximum current the output can sink in LOW state while still maintaining the output voltage below VO_Lmax.
I_Imax : The maximum current that flows into an input in any state (1ƒIA for CMOS).

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../images/main/bullet_star_pink.gif Noise Margin

Gate circuits are constructed to sustain variations in input and output voltage levels. Variations are usually the result of several different factors.

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Batteries lose their full potential, causing the supply voltage to drop
High operating temperatures may cause a drift in transistor voltage and current characteristics
Spurious pulses may be introduced on signal lines by normal surges of current in neighbouring supply lines.

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All these undesirable voltage variations that are superimposed on normal operating voltage levels are called noise. All gates are designed to tolerate a certain amount of noise on their input and output ports. The maximum noise voltage level that is tolerated by a gate is called noise margin. It derives from I/P-O/P voltage characteristic, measured under different operating conditions. It's normally supplied from manufacturer in the gate documentation.

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LNM (Low noise margin): The largest noise amplitude that is guaranteed not to change the output voltage level when superimposed on the input voltage of the logic gate (when this voltage is in the LOW interval). LNM=VI_Lmax-VO_Lmax.
HNM (High noise margin): The largest noise amplitude that is guaranteed not to change the output voltage level if superimposed on the input voltage of the logic gate (when this voltage is in the HIGH interval). HNM=VO_Hmin-VI_Hmin

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../images/main/bullet_star_pink.gif tr (Rise time)

The time required for the output voltage to increase from VILmax to VIHmin.

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../images/main/bullet_star_pink.gif tf (Fall time)

The time required for the output voltage to decrease from VIHmin to VILmax.

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../images/main/bullet_star_pink.gif tp (Propagation delay)

The time between the logic transition on an input and the corresponding logic transition on the output of the logic gate. The propagation delay is measured at midpoints.

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../images/main/bullet_star_pink.gif Power Dissipation.

Each gate is connected to a power supply VCC (VDD in the case of CMOS). It draws a certain amount of current during its operation. Since each gate can be in a High, Transition or Low state, there are three different currents drawn from power supply.

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ICCH: Current drawn during HIGH state.
ICCT: Current drawn during HIGH to LOW, LOW to HIGH transition.
ICCL: Current drawn during LOW state.

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For TTL, ICCT the transition current is negligible, in comparison to ICCH and ICCL. If we assume that ICCH and ICCL are equal then,

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Average Power Dissipation = Vcc * (ICCH + ICCL)/2

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For CMOS, ICCH and ICCL current is negligible, in comparison to ICCT. So the Average power dissipation is calculated as below.

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Average Power Dissipation = Vcc * ICCT.

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So for TTL like logics family, power dissipation does not depend on frequency of operation, and for CMOS the power dissipation depends on the operation frequency.

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Power Dissipation is an important metric for two reasons. The amount of current and power available in a battery is nearly constant. Power dissipation of a circuit or system defines battery life: the greater the power dissipation, the shorter the battery life. Power dissipation is proportional to the heat generated by the chip or system; excessive heat dissipation may increase operating temperature and cause gate circuitry to drift out of its normal operating range; will cause gates to generate improper output values. Thus power dissipation of any gate implementation must be kept as low as possible.

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Moreover, power dissipation can be classified into Static power dissipation and Dynamic power dissipation.

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Ps (Static Power Dissipation): Power consumed when the output or input are not changing or rather when clock is turned off. Normally static power dissipation is caused by leakage current. (As we reduce the transistor size, i.e. below 90nm, leakage current could be as high as 40% of total power dissipation).
Pd (Dynamic Power Dissipation): Power consumed during output and input transitions. So we can say Pd is the actual power consumed i.e. the power consumed by transistors + leakage current.

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Thus

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Total power dissipation = static power dissipation + dynamic power dissipation.

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Do you have any Comment? mail me at:deepak@asic-world.com