Digital Questions

Digital Questions

Jan-7-2025

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Sample Digital Questions Asked in Interviews. Please contribute your questions. If you are looking for answers please refer to website FAQ

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../images/main/bullet_4dots_green.gif What is the output of AND gate in the circuit below, when A and B are as in waveform? Tp is the gate delay of respective gate.

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../images/main/bullet_4dots_green.gif Identify the circuit below, and its limitation.

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../images/digital/question_parity.gif

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../images/main/bullet_4dots_green.gif What is the current through the resistor R1 (Ic) ?

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../images/digital/question_transistor.gif

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../images/main/bullet_4dots_green.gif Referring to the diagram below, briefly explain what will happen if the propagation delay of the clock signal in path B is much too high compared to path A. How do we solve this problem if the propagation delay in path B can not be reduced ?

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../images/digital/question_ff_delay.gif

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../images/main/bullet_4dots_green.gif What is the function of a D flip-flop, whose inverted output is connected to its input ?

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../images/main/bullet_4dots_green.gif Design a circuit to divide input frequency by 2.

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../images/main/bullet_4dots_green.gif Design a divide-by-3 sequential circuit with 50% duty cycle.

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../images/main/bullet_4dots_green.gif Design a divide-by-5 sequential circuit with 50% duty cycle.

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../images/main/bullet_4dots_green.gif What are the different types of adder implementations ?

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../images/main/bullet_4dots_green.gif Draw a Transmission Gate-based D-Latch.

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../images/main/bullet_4dots_green.gif Give the truth table for a Half Adder. Give a gate level implementation of it.

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../images/main/bullet_4dots_green.gif What is the purpose of the buffer in the circuit below, is it necessary/redundant to have a buffer ?

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../images/main/bullet_4dots_green.gif What is the output of the circuit below, assuming that value of 'X' is not known ?

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../images/digital/question_xor.gif

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../images/main/bullet_4dots_green.gif Consider a circular disk as shown in the figure below with two sensors mounted X, Y and a blue shade painted on the disk for an angle of 45 degree. Design a circuit with minimum number of gates to detect the direction of rotation.

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../images/main/bullet_4dots_green.gif Design an OR gate from 2:1 MUX.

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../images/main/bullet_4dots_green.gif Design an XOR gate from 2:1 MUX and a NOT gate

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../images/main/bullet_4dots_green.gif What is the difference between a LATCH and a FLIP-FLOP ?

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Latch is a level sensitive device while flip-flop is an edge sensitive device.
Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to glitches.
Latches take less gates (also less power) to implement than flip-flops.
Latches are faster than flip-flops.

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../images/main/bullet_4dots_green.gif Design a D Flip-Flop from two latches.

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../images/main/bullet_4dots_green.gif Design a 2 bit counter using D Flip-Flop.

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../images/main/bullet_4dots_green.gif What are the two types of delays in any digital system ?

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../images/main/bullet_4dots_green.gif Design a Transparent Latch using a 2:1 Mux.

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../images/digital/mux_latch.gif

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../images/main/bullet_4dots_green.gif Design a 4:1 Mux using 2:1 Muxes and some combo logic.

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../images/main/bullet_4dots_green.gif What is metastable state ? How does it occur ?

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../images/main/bullet_4dots_green.gif What is metastability ?

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../images/main/bullet_4dots_green.gif Design a 3:8 decoder

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../images/main/bullet_4dots_green.gif Design a FSM to detect sequence "101" in input sequence.

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../images/main/bullet_4dots_green.gif Convert NAND gate into Inverter, in two different ways.

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../images/main/bullet_4dots_green.gif Design a D and T flip flop using 2:1 mux; use of other components not allowed, just the mux.

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../images/main/bullet_4dots_green.gif Design a divide by two counter using D-Latch.

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../images/main/bullet_4dots_green.gif Design D Latch from SR flip-flop.

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../images/main/bullet_4dots_green.gif Define Clock Skew , Negative Clock Skew, Positive Clock Skew.

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../images/main/bullet_4dots_green.gif What is Race Condition ?

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../images/main/bullet_4dots_green.gif Design a 4 bit Gray Counter.

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../images/main/bullet_4dots_green.gif Design 4-bit Synchronous counter, Asynchronous counter.

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../images/main/bullet_4dots_green.gif Design a 16 byte Asynchronous FIFO.

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../images/main/bullet_4dots_green.gif What is the difference between an EEPROM and a FLASH ?

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../images/main/bullet_4dots_green.gif What is the difference between a NAND-based Flash and a NOR-based Flash ?

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../images/main/bullet_4dots_green.gif You are given a 100 MHz clock. Design a 33.3 MHz clock with and without 50% duty cycle.

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../images/main/bullet_4dots_green.gif Design a Read on Reset System ?

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../images/main/bullet_4dots_green.gif Which one is superior: Asynchronous Reset or Synchronous Reset ? Explain.

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../images/main/bullet_4dots_green.gif Design a State machine for Traffic Control at a Four point Junction.

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../images/main/bullet_4dots_green.gif What are FIFO's? Can you draw the block diagram of FIFO? Could you modify it to make it asynchronous FIFO ?

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../images/main/bullet_4dots_green.gif How can you generate random sequences in digital circuits?

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Do you have any Comment? mail me at:deepak@asic-world.com