| author | Felix Salfelder <felix@salfelder.org> | 2025年11月09日 00:00:00 +0000 |
|---|---|---|
| committer | Felix Salfelder <felix@salfelder.org> | 2025年11月09日 00:00:00 +0000 |
| commit | 7c6b160441b25a87d1214283c6c2833be6a45664 (patch) | |
| tree | ec23df41330e669e1911109cc7f235a6ac27d28a | |
| parent | b3e210338c7a7f41ebdd7a0478808b434d36da2c (diff) | |
| download | gnucap-7c6b160441b25a87d1214283c6c2833be6a45664.tar.gz | |
| -rw-r--r-- | tests/==out/lang_verilog.dup.0.gc.out | 10 | ||||
| -rw-r--r-- | tests/lang_verilog.dup.0.gc | 17 |
diff --git a/tests/==out/lang_verilog.dup.0.gc.out b/tests/==out/lang_verilog.dup.0.gc.out new file mode 100644 index 00000000..e58a526c --- /dev/null +++ b/tests/==out/lang_verilog.dup.0.gc.out @@ -0,0 +1,10 @@ + r2 #(.r(300)) r2(a,b); + ^ ? aaa.r2: already set r, ignored +module aaa (.a(a),.b(b)); +resistor #(.r(100)) r1 (.p(a),.n(b)); +resistor #(.r(100)) r2 (.p(a),.n(b)); +resistor #(.r(100)) r2 (.p(a),.n(b)); +endmodule // aaa + +# v(a) + 0. 33.333 diff --git a/tests/lang_verilog.dup.0.gc b/tests/lang_verilog.dup.0.gc new file mode 100644 index 00000000..f87e81ee --- /dev/null +++ b/tests/lang_verilog.dup.0.gc @@ -0,0 +1,17 @@ +verilog + +module aaa (a,b); + resistor #(100) r1(a,b); + r1 #() r2(a,b); + r2 #(.r(300)) r2(a,b); +endmodule; + +list + +aaa a1(0円 , a); +isource #(.dc(1)) i1(0円 , a); + +print dc v(a) +dc + +end |