This project was an excuse to learn about Verilog and programmable parts (cpld, fpga). I chose this project because someone asked about it on Usenet, and the generic response was "use a ROM" - but to get a ROM wide enough would have been expensive, and wasteful - most ROMs these days have many inputs and 8 outputs, we want one with few inputs and many outputs - 8 (or more) in and 21 out. I suggested a 1ドル CPLD instead (turns out you need a 2ドル CPLD), then decided to actually make one to see if it would work.
While this project doesn't fit in the 9536 (smallest) CPLD, it does fit in the 9572 one, meaning the chip only costs 2ドル (instead of 1ドル for the smaller part), in single quantities. In the photo above you can see the chip in a test harness (right), along with the JTAG module for my USB pod (left top) and a spare R8C/27 chip (left bottom).
| Inputs | |
|---|---|
| BIN[0:7] | The 8-bit binary input. This is unsigned, and represents values from 0 to 255. |
| EN EN | Enable inputs. If EN is low and EN is high, the outputs follow the inputs. Otherwise, the outputs remain unchanged. Note that these signals latch the input value, not the result of applying the other inputs to it. |
| BLANK | If high, all outputs are tri-stated. |
| LZBLANK | If high, leading zeros are tri-stated, otherwise leading zeros are displayed. |
| POLARITY | If low, output lines are high for "on" segments. If high, output lines are low for "on" segments. |
| Outputs | |
| SEG0[a:g], SEG1[a:g], SEG2[a:g] | Output segments, seven per digit (seg2 is the MSB). These outputs are either high, low, or high-Z (for blanking). |
