Advanced Interrupt Architecture
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The Advanced Interrupt Architecture (AIA) is a specification for handling interrupts on RISC-V platforms. It is more advanced than the PLIC, supporting features such as MSI which are unsupported by PLIC.
CSRs
AIA adds the following CSRs:
Machine-Level Window to Indirectly Accessed Registers
| Number | Read/Write | Width (bits) | Name | Description |
|---|---|---|---|---|
| 0x350 | MRW | XLEN | miselect
|
|
| 0x351 | MRW | XLEN | mireg
|
Supervisor-Level Window to Indirectly Accessed Registers
| Number | Read/Write | Width (bits) | Name | Description |
|---|---|---|---|---|
| 0x150 | SRW | XLEN | siselect
|
Supervisor indirect register select |
| 0x151 | SRW | XLEN | sireg
|
Supervisor indirect register alias |
Supervisor-Level Interrupts
| Number | Read/Write | Width (bits) | Name | Description |
|---|---|---|---|---|
| 0x104 | SRW | 64 | sie
|
Supervisor interrupt-enable bits |
| 0x144 | SRW | 64 | sip
|
Supervisor interrupt-pending bits |
| 0x15C | SRW | SXLEN | stopei
|
Supervisor top external interrupt (only with an IMSIC) |
| 0xDB0 | SRO | SXLEN | stopi
|
Supervisor top interrupt |
| 0x114 | SRW | 32 | sieh
|
Upper 32 bits of sie (RV32 only)
|
| 0x154 | SRW | 32 | siph
|
Upper 32 bits of sip (RV32 only)
|
APLIC (Advanced Platform-Level Interrupt Controller)
IMSIC (Incoming Message-Signaled Interrupt Controller)
As the name implies, the IMSIC is designed to convert MSI notifications into interrupts.
Each IMSIC is associated with a single hart. An IMSIC consists of one or more interrupt files, at least one for each privilege level (except U-mode(?)). Each interrupt file corresponds to a single interrupt vector, but MSIs from multiple sources can be distinguished by identity numbers.
An interrupt file is always aligned on a 4-KiB (page) boundary. Only two 32-bit registers are specified:
| Offset | Name | Description |
|---|---|---|
0x000
|
seteipnum_le
|
For little-endian systems |
0x004
|
seteipnum_be
|
For big-endian systems |
Writing a value i will set the pending bit of identity number i.
CSRs
These CSRs are indirectly accessed by first writing *iselect and then reading or writing *ireg.
| ID | Name |
|---|---|
0x70
|
eidelivery
|
0x72
|
eithreshold
|
0x80
|
eip0
|
0x81
|
eip1
|
| ... | ... |
0xBF
|
eip63
|
0xC0
|
eie0
|
0xC1
|
eie1
|
| ... | ... |
0xFF
|
eie63
|