Paging: Difference between revisions

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==MMU==
==MMU==
Paging is achieved through the use of the [[MMU]]. The MMU is a unit that (削除) wonderfully (削除ここまで)transforms virtual addresses into physical addresses based on the current (削除) paging (削除ここまで)table.
Paging is achieved through the use of the [[MMU]]. The MMU is a unit that transforms virtual addresses into physical addresses based on the current (追記) page (追記ここまで)table(追記) .This section focuses on the x86 MMU (追記ここまで).


===(削除) Relaxed Technical Overview (削除ここまで)===
===(追記) Page Directory (追記ここまで)===
(削除) Think of your RAM (削除ここまで). It is (削除) probably several hundred megabytes (削除ここまで)of (削除) continuous non-volatile memory. Now, imagine (削除ここまで)that (削除) it is actually 4 gigabytes. This is what the MMU is paid to do with a little help from (削除ここまで)the (削除) kernel (削除ここまで).
(追記) The topmost paging structure is the page directory (追記ここまで). It is (追記) essentially an array (追記ここまで)of (追記) page directory entries (追記ここまで)that (追記) take (追記ここまで)the (追記) following form (追記ここまで).


(削除) In a 32bit Intel x86 CPU (削除ここまで), (削除) there (削除ここまで)are (削除) 2 types of tables. There are the: (削除ここまで)
(追記) '''Note: With 5mb pages (追記ここまで), (追記) bits 21 through 12 (追記ここまで)are (追記) Reserved!''' (追記ここまで)
(削除) i* Page Directory (削除ここまで)
(削除) * Page Tables (削除ここまで)


(削除) Knowing this, there are some simple rules, if you will (削除ここまで):
(追記) [[Image (追記ここまで):(追記) Page dir (追記ここまで).(追記) png|frame|A Page Table Entry]] (追記ここまで)
(削除) * There is only one page directory in use at any one time. (削除ここまで)
(削除) * Each structure consumes 4kb of space. (削除ここまで)
(削除) * Each entry in each structure is 4bytes in size (削除ここまで).


(追記) The page table address field represents the physical address of the page table that managers the four megabytes at that point. Please note that it is very important that this address be 4kb aligned. This is needed, due to the fact that the last bits of the dword are overwritten by access bits and such. (追記ここまで)


(削除) If you will recall (削除ここまで), (削除) we know (削除ここまで)that the (削除) MMU (削除ここまで)is (削除) made to map x number of megabytes to 4 gigabytes (削除ここまで). (削除) Considering this (削除ここまで), (削除) we can now figure out how physical memory is mapped (削除ここまで).
(追記) The next valid flag, S, or 'Page Size' (追記ここまで), (追記) stores the page size for (追記ここまで)that (追記) specific entry. If (追記ここまで)the (追記) bit (追記ここまで)is (追記) set, then pages are 4mb in size (追記ここまで). (追記) Otherwise (追記ここまで), (追記) they are 4kb (追記ここまで).


(削除) * (削除ここまで)page (削除) directory size = 4096 bytes (削除ここまで)
(追記) A, or 'Accessed' is used to discover whether a (追記ここまで)page (追記) has been read or written to. If it has, then the bit is set, otherwise, it is not. Note that, this bit will not be cleared by the CPU, so that burden falls on the OS. (追記ここまで)((追記) ie (追記ここまで). (追記) if it needs this bit at all (追記ここまで).)
(削除) *page entry = 4 bytes (削除ここまで)
(削除) *number of directory entries = 4096/4 = 1024 (削除ここまで)
(削除) *number of table entries = directory entries = 1024 (削除ここまで)
(削除) *mapped RAM per directory entry (削除ここまで)((削除) aka (削除ここまで). (削除) a table) = 4gb/1024 = 4mb (削除ここまで)
(削除) *mapped RAM per table entry (aka (削除ここまで). (削除) a page (削除ここまで)) (削除) = 4mb/1024 = 4kb. (削除ここまで)


(削除) There you have it (削除ここまで). (削除) Each ' (削除ここまで)page(削除) ' is then 4kb (削除ここまで).
(追記) D, is the 'Cache Disable' bit (追記ここまで). (追記) If set, the (追記ここまで)page (追記) will not be cached. Otherwise, it will be (追記ここまで).


(追記) W, the controls 'Write-Through' abilities of the page. If the bit is set, write-through caching is enabled. If not, then write-back is enabled instead. (追記ここまで)


(削除) The structure of (削除ここまで)the (削除) above in computer speak is quite simple. Each entry is (削除ここまで)the (削除) address of it's child (削除ここまで). If (削除) it's a directory entry (削除ここまで), the (削除) entry consists of (削除ここまで)the (削除) table's address. Moreover (削除ここまで), (削除) if it's a table's entry we're talking about (削除ここまで), (削除) then (削除ここまで)it(削除) 's the the address of the mapped physical memory (削除ここまで).
(追記) U, (追記ここまで)the (追記) user\supervisor bit, controls access to (追記ここまで)the (追記) page based on privilege level (追記ここまで). If (追記) the bit is set (追記ここまで), (追記) then (追記ここまで)the (追記) page may be accessed by all; if (追記ここまで)the (追記) bit is not set (追記ここまで), (追記) however (追記ここまで), (追記) only the supervisor can access (追記ここまで)it.


(削除) A short note (削除ここまで), (削除) however (削除ここまで), (削除) just to ruin your simplicity. Each entry described above also contains several flags. As this (削除ここまで)is (削除) a relaxed overview (削除ここまで), (削除) I'll only list the three major ones here: (削除ここまで)
(追記) R (追記ここまで), (追記) the read and write permissions flag (追記ここまで), (追記) either makes the page only readable, that (追記ここまで)is, (追記) when it is not (追記ここまで)set, (追記) or makes (追記ここまで)the (追記) page both readable and writable, (追記ここまで)that is(追記) , being set (追記ここまで).
(削除) *Bits 31-12: 4kb aligned address of entry (削除ここまで)
(削除) *Bit 2: User\Supervisor (削除ここまで)
(削除) *Bit 1: Read\Write (削除ここまで)
(削除) *Bit 0: Presence Flag - While (削除ここまで)set, the (削除) MMU will assume (削除ここまで)that (削除) this page (削除ここまで)is (削除) currently in memory (削除ここまで).


(削除) Have you made (削除ここまで)the (削除) connection? Each (削除ここまで)page is (削除) 4kb (削除ここまで), and (削除) each entry's address must be 4kb aligned! It's just clicking, isn't (削除ここまで)it(削除) ? (削除ここまで)
(追記) P, or 'Presence', determines if the page is actually in physical memory at (追記ここまで)the (追記) moment. (eg. if a page only exists on the hard drive, it is not in physical memory.) If a (追記ここまで)page is (追記) called, but not present, a page fault will occur (追記ここまで), and (追記) the OS should handle (追記ここまで)it(追記) . (See below.) (追記ここまで)
(追記) ===Page Table=== (追記ここまで)
(追記) Todo (追記ここまで)


====Example====
====Example====

Revision as of 20:00, 15 November 2007

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Overview

Paging is a memory scheme that breaks up memory in groups of pages that are constantly swapped between hard disk and computer. This allows for one to appear as though they have more memory than they actually do.

MMU

Paging is achieved through the use of the MMU. The MMU is a unit that transforms virtual addresses into physical addresses based on the current page table.This section focuses on the x86 MMU.

Page Directory

The topmost paging structure is the page directory. It is essentially an array of page directory entries that take the following form.

Note: With 5mb pages, bits 21 through 12 are Reserved!

A Page Table Entry

The page table address field represents the physical address of the page table that managers the four megabytes at that point. Please note that it is very important that this address be 4kb aligned. This is needed, due to the fact that the last bits of the dword are overwritten by access bits and such.

The next valid flag, S, or 'Page Size', stores the page size for that specific entry. If the bit is set, then pages are 4mb in size. Otherwise, they are 4kb.

A, or 'Accessed' is used to discover whether a page has been read or written to. If it has, then the bit is set, otherwise, it is not. Note that, this bit will not be cleared by the CPU, so that burden falls on the OS. (ie. if it needs this bit at all.)

D, is the 'Cache Disable' bit. If set, the page will not be cached. Otherwise, it will be.

W, the controls 'Write-Through' abilities of the page. If the bit is set, write-through caching is enabled. If not, then write-back is enabled instead.

U, the user\supervisor bit, controls access to the page based on privilege level. If the bit is set, then the page may be accessed by all; if the bit is not set, however, only the supervisor can access it.

R, the read and write permissions flag, either makes the page only readable, that is, when it is not set, or makes the page both readable and writable, that is, being set.

P, or 'Presence', determines if the page is actually in physical memory at the moment. (eg. if a page only exists on the hard drive, it is not in physical memory.) If a page is called, but not present, a page fault will occur, and the OS should handle it. (See below.)

Page Table

Todo

Example

Say I loaded my kernel to 0x100000. However, I want it mapped to 0xc0000000. After loading my kernel, I initiate paging, and set up the appropriate tables. (See Higher Half Kernel) After Identity Paging the first megabyte, I start to create my second table (ie. at entry #768 in my directory.) to map 0x100000 to 0xc0000000. My code could be like:

mov eax, 0x0
mov ebx, 0x100000
.fill_table:
 mov ecx, ebx
 or ecx, 3
 mov [table_768+eax*4], ecx
 add ebx, 4096
 inc eax
 cmp eax, 1024
 je .end
 jmp .fill_table
.end:	

Enabling

Enabling paging is actually very simple. All that is needed is to load CR3 with the address of the page directory and to set the paging bit of CR0.

mov eax, [page_directory]
mov cr3, eax
mov eax, cr0
or eax, 0x80000000
mov cr0, eax

Usage

Todo

Page Faults

A page fault is an exception caused when a process is seeking to access an area of virtual memory that is not mapped to any physical memory.

Handling

Todo

See Also

Articles

External Links

Paging Tutorial

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