Announcement: IdealOS
- Alexey1994
- Member
Member - Posts: 63
- Joined: Sat Jan 28, 2023 11:41 am
- Location: Belarus
- Contact:
Re: Announcement: IdealOS
Post by Alexey1994 »
I received an interesting notification from the administration. It turns out they doubt my competence. Well, let them try to prove it on the merits. Of course, I don't understand why I can be humiliated in my personal post, but I can't respond to it. There's no point in me posting code here anyway. This is a dump of possibly good projects, but not a space for creativity, this is well described in the FAQ. If the sophists win in my personal post, it will be a wonderful precedent. I will not allow anyone to humiliate me in any way, either directly or indirectly. This is an axiom. Especially in my own post.
Re: Announcement: IdealOS
I hate dealing with issues in the view of others, but your warning has nothing to do with competence. It is simply because I wanted to remind you of the forum rules, which you have broken two of in this thread. Obviously iansjack hasn't dragged himself into a fight with you (thankfully), but I don't believe it sets a good precedent to let new members speak disrespectfully to senior forum members, and so I warned you.
- Alexey1994
- Member
Member - Posts: 63
- Joined: Sat Jan 28, 2023 11:41 am
- Location: Belarus
- Contact:
Re: Announcement: IdealOS
Post by Alexey1994 »
Here I clearly show how Nasm creates a longer opcode for no reason
https://youtu.be/pOpN2ogCb90
- MichaelPetch
- Member
Member - Posts: 853
- Joined: Fri Aug 26, 2016 1:41 pm
- Libera.chat IRC: mpetch
Re: Announcement: IdealOS
Post by MichaelPetch »
Code: Select all
use32
inc dword [eax+ebp]
inc dword [ebp+eax]Code: Select all
00000000 FF0428 inc dword [eax+ebp]
00000003 FF440500 inc dword [ebp+eax+0x0]Right now your assembler is crap because it has been programmed by someone who lacks an understanding in basic x86 design especially scale*index+base+displacement addressing. Even the competent 13-14 year old OS Developers on this forum already understand the difference.
What do I know though, you think I am just stupid.
- Octocontrabass
- Member
Member - Posts: 6025
- Joined: Mon Mar 25, 2013 7:01 pm
Re: Announcement: IdealOS
Post by Octocontrabass »
But you said there were lots of bugs. What else have you found?
- MichaelPetch
- Member
Member - Posts: 853
- Joined: Fri Aug 26, 2016 1:41 pm
- Libera.chat IRC: mpetch
Re: Announcement: IdealOS
Post by MichaelPetch »
- Alexey1994
- Member
Member - Posts: 63
- Joined: Sat Jan 28, 2023 11:41 am
- Location: Belarus
- Contact:
Re: Announcement: IdealOS
Post by Alexey1994 »
Code: Select all
use32
inc dword [eax+ebp]
inc dword [ebp+eax]Code: Select all
00000000 FF0428 inc dword [eax+ebp]
00000003 FF440500 inc dword [ebp+eax+0x0]Right now your assembler is crap because it has been programmed by someone who lacks an understanding in basic x86 design especially scale*index+base+displacement addressing. Even the competent 13-14 year old OS Developers on this forum already understand the difference.
What do I know though, you think I am just stupid.
https://github.com/sarah-walker-pcem/pc ... /386.c#L22
And at the same time you ignore the fact that this assembler is made specifically for my operating system, in which all segments are equal. And such an assembler can be useful to everyone who writes their own OS and does not want your name to appear there as a developer. Well, okay, not everyone can understand this. If you want bugs, then read the topic above, nasm generates short addresses in certain situations, but not in all. The justification by alignment will not work - there is no alignment there.
And share a link to your operating system, please.
- Octocontrabass
- Member
Member - Posts: 6025
- Joined: Mon Mar 25, 2013 7:01 pm
Re: Announcement: IdealOS
Post by Octocontrabass »
[引用]
[引用]
- MichaelPetch
- Member
Member - Posts: 853
- Joined: Fri Aug 26, 2016 1:41 pm
- Libera.chat IRC: mpetch
Re: Announcement: IdealOS
Post by MichaelPetch »
NASM assumes an effective address (EA) is of the form disp[base+index*scale] (where some components can be omitted). `inc dword [eax+ebp]` is disp=0, base=eax, index=ebp, and scale=1. `inc dword [ebp+eax]` is disp=0, base=ebp, index=eax, and scale=1. The problem here is that if the CPU encounters a BASE with register ESP or EBP the Stack Segment is the default, not the Data Segment. Volume 1 of the Intel SDM section 3.7.5 provides this rule:
The NASM documentation has documented this situation in Section 3.3:The uses of general-purpose registers as base or index components are restricted in the following manner:
• The ESP register cannot be used as an index register.
• When the ESP or EBP register is used as the base, the SS segment is the default segment. In all other cases,
the DS segment is the default segment.
If EBP is the index then the default segment is DS. If EBP is the base then the default segment is SS. So to NASM it matters whether something may be the base or index in the effective address. Note: If you attempt to illegally use ESP as an index (with a scale of 1) NASM will swap and make ESP the base and the other register the index. An attempt to apply scale >1 to ESP is invalid and NASM will warn you.NASM has a hinting mechanism which will cause [eax+ebx] and [ebx+eax] to generate different opcodes; this is occasionally useful because [esi+ebp] and [ebp+esi] have different default segment registers.
You claimed that NASM has bugs. We don't know what the intentions of your own assembler are (unless you tell us) or if we actually knew the design of your OS which we don't. NASM producing a 3 byte instruction vs 4 byte is not about alignment in this case. It is about what default segment the CPU will use. When SS.base != DS.base then these are not equivalent from the CPU perspective:
Code: Select all
inc dword [eax+ebp]
inc dword [ebp+eax]Code: Select all
inc dword ss:[eax+ebp]Your assembler has no documentation and there is nothing saying what its expectations are. Your assembler as is would not be useful for encoding in environments where SS.base and DS.base are not the same which is often the case in 16-bit real and 16-bit protected mode. It is a deficiency in your assembler that doesn't make it generic. That is not how NASM was designed, as it is trying to be environmentally agnostic.
If you think that NASM is generating less than efficient instruction encodings it is far more likely that NASM understands the nuances of the x86 instruction encodings better than you do - and what you perceive to be a bug is actually by design. Most of the time NASM bugs are not related to basic instruction encodings. I found a bug in the Macho64 object metadata and it was eventually fixed by NASM developers.
The STRICT keyword in NASM can sometimes be used to generate a specific instruction encoding that may not been the default.
- Alexey1994
- Member
Member - Posts: 63
- Joined: Sat Jan 28, 2023 11:41 am
- Location: Belarus
- Contact:
Re: Announcement: IdealOS
Post by Alexey1994 »
better.png
[引用]
Re: Announcement: IdealOS
Teenagers are always free to make fools of themselves but, if I wasn’t involved, I would lock this thread now.