6097 – SSSE3 instructions in inline assembler cause error using DMD from git master

Created attachment 991 [details] 
Patch with instruction size information for 3 byte opcodes
In the inline assembler, SSSE3 instructions produce an error if used with MMX
registers. E.g. the program
void main()
{
 asm {
 pshufb MM0, MM1;
 }
}
causes the following error message:
actual: 3, calc: 5
code 003E0A08: nxt=00000000 op=f38 flg=40 rm=c1=3,0,1
Internal error: backend\cod3.c 4448
Everything seems to work if you use only XMM registers.
The root cause seems to be that there is no instruction size stored for 3 byte
opcodes (opcodes starting with 0F 38 and 0F 3A).
The attached patch tries to correct the problem. With the patch applied, some
more instructions could be added to the inline assembler (popcnt, crc32,
movbe).

Hello, your patch breaks the mandatory prefix check for 2 byte ops such as
PXOR 66 0F EF /r ( SSE2 )
I've edited your patch and included SSE4.1 and 4.2 sizes as well as proper REX prefix for 4 byte ops (PEXTRQ/PINSRQ)
I also cleaned up the table so that exceptions to the default size would stand out more by glancing at the code. ( hope you like it :P )
I have a branch with sse4_1 added in my fork on github, but I've not tested it enough to be confident to issue a pull request.
https://github.com/Govelius/dmd/commits/sse4_1 

Created attachment 993 [details] 
kai@redstar.de patch + fixes
Includes kai@redstar.de patch + additional fixes

https://github.com/D-Programming-Language/dmd/commit/d3f5c9c2bd143bc0037640465250603b244431c7
https://github.com/D-Programming-Language/dmd/commit/9a8b9b12386cef1a4423bfc14ea3159a50e2623a