The QUICC Engine provides interrupts for a few I/O ports. This is handled via a separate interrupt ID and managed via a triplet of dedicated registers hosted by the SoC. Implement an interrupt driver for those IRQs then add IRQs capability to the QUICC ENGINE GPIOs. The number of GPIOs for which interrupts are supported depends on the microcontroller: - mpc8323 has 10 GPIOS supporting interrupts - mpc8360 has 28 GPIOS supporting interrupts - mpc8568 has 18 GPIOS supporting interrupts Changes in v2: - Fixed warning on PPC64 build (Patch 1) - Using devm_kzalloc() instead of kzalloc (Patch 2) - Stop using of-mm-gpiochip (New patch 3) - Added fsl,qe-gpio-irq-mask propertie in DT binding doc (Patch 4) - Fixed problems reported by 'make dt_binding_check' (Patch 5) Christophe Leroy (5): soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports soc: fsl: qe: Change GPIO driver to a proper platform driver soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver soc: fsl: qe: Add support of IRQ in QE GPIO dt-bindings: soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports .../soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml | 58 +++++++ .../bindings/soc/fsl/cpm_qe/qe/par_io.txt | 19 +++ arch/powerpc/platforms/Kconfig | 1 - drivers/soc/fsl/qe/Makefile | 2 +- drivers/soc/fsl/qe/gpio.c | 145 +++++++++------- drivers/soc/fsl/qe/qe_ports_ic.c | 156 ++++++++++++++++++ 6 files changed, 322 insertions(+), 59 deletions(-) create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml create mode 100644 drivers/soc/fsl/qe/qe_ports_ic.c -- 2.49.0