DOI:10.1007/978-3-319-78890-6_49 - Corpus ID: 19089600
Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks for Quantum Computing Systems
@inproceedings{Pfau2018ReconfigurableFC,
title={Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks for Quantum Computing Systems},
author={Johannes Pfau and Shalina Percy Delicia Figuli and Steffen B{\"a}hr and J{\"u}rgen Becker},
booktitle={International Workshop on Applied Reconfigurable Computing},
year={2018},
url={https://api.semanticscholar.org/CorpusID:19089600}
}- J. Pfau S. P. D. Figuli J. Becker
- Published in International Workshop on... 2 May 2018
- Computer Science, Engineering, Physics
A low latency, adaptable, FPGA-based channelizer using the Polyphase Filter Bank (PFB) signal processing algorithm is presented, allowing the user to select from different numbers of channels, sample bit widths and throughput specifications.
6 Citations
Topics
Latency (opens in a new tab) Polyphase Filter Banks (opens in a new tab) Output Channel (opens in a new tab) Quantum Systems (opens in a new tab) Field Programmable Gate Array (opens in a new tab) Reconfigurable (opens in a new tab) Hardware Resources (opens in a new tab) Data Rates (opens in a new tab)
6 Citations
A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC
- J. Smith John I. Bailey B. Mazin
- 2021
Engineering, Computer Science
The design and implementation of a 4 GHz, 4096-branch, 8-tap, 2/1 oversampled polyphase channelizer implemented on a Xilinx RFSoC is reported, providing the first example of an oversampling poly phase channelizer running on a system on a chip architecture created without direct use of hardware description language.
Low-cost, High-speed Parallel FIR Filters for RFSoC Front-Ends Enabled by CλaSH
- C. Ramsay L. Crockett R. Stewart
- 2021
Engineering, Computer Science
We present a new low-cost, high-speed parallel FIR filter generator targeting the Xilinx Radio Frequency System on Chip (RFSoC) and direct RF sampling applications. We compose two existing approaches...
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- Christiaan Boerkamp S. V. D. Vlugt Zaid Al-Ars
- 2024
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This paper introduces TINA, a novel framework for implementing non Neural Network (NN) signal processing algorithms on NN accelerators such as GPUs, TPUs or FPGAs, and shows that TINA is highly competitive vs alternative frame-works, specifically for complex functions with iterations.
Exploring the Versal AI Engines for Signal Processing in Radio Astronomy
- Victor Van Wijhe Vincent Sprave S. V. D. Vlugt
- 2024
Engineering, Physics
This work explores the AIEs to evaluate their capabilities for real-time signal processing in radio telescope systems, and develops an efficient PFB implementation that requires only 12 AIEs.
Real-Time Graph Building on FPGAs for Machine Learning Trigger Applications in Particle Physics
- Marc Neu Juergen Becker K. Unger
- 2024
Physics, Computer Science
By enabling an hardware-accelerated preprocessing of graphs, this work enables the deployment of novel Graph Neural Networks (GNNs) in first-level triggers of particle physics experiments and proves that the automated methodology generates online graph building designs suitable for a wide range of particle physics applications.
Modeling and implementing the behavior of RR robot using FPGA
- M. AlShabi Talal Bonny
- 2022
Engineering, Computer Science
Defense + Commercial Sensing
In this paper, the mathematical model of a non-linear RR manipulator is developed, and the circuit design of the system is described first in detail, and then implemented on the FPGA (field programmer gate array) prototyping board.
17 References
A novel system on chip for software-defined, high-speed OFDM signal processing
- Joachim Meyer M. Dreschmann J. Becker
- 2013
Computer Science, Engineering
A novel system on chip (SoC) that is especially developed for digital signal processing of high-speed orthogonal frequency division multiplexing (OFDM) signals with data rates up to gigabits per second is described.
FPGA realization of GDFT-FB based channelizers
- Fangzhou Wu Álvaro Palomo-Navarro Rudi C. Villing
- 2015
Computer Science, Engineering
This work examines the design and implementation of the fundamental DFT-FB and GDFT-FB on an FPGA in both critically sampled and oversampled variants and solutions to various design issues are presented.
FPGA based FRM GDFT filter banks
- Fangzhou Wu Rudi C. Villing
- 2016
Computer Science, Engineering
This work examines the design and implementation of the full FRM GDFT-FB and narrowband FRM gFT modulated Filter Bank on an FPGA and describes solutions to various design issues encountered and evaluates the DSP performance and the FPGa resource usage using a concrete channelization problem based on TETRA 25 kHz channels.
Digital receivers and transmitters using polyphase filter banks for wireless communications
Provides a tutorial overview of multichannel wireless digital receivers and the relationships between channel bandwidth, channel separation, and channel sample rate. The overview makes liberal use of...
Compensating for oversampling effects in polyphase channelizers: A radio astronomy application
- J. Tuthill G. Hampson T. Bateman
- 2015
Engineering, Physics
2015 IEEE Signal Processing and Signal Processing...
The structure of the oversampled polyphase filterbank used for the new Australian Square Kilometer Array Pathfinder (ASKAP) radio telescope is presented and a technique used to correct for the sub-band frequency shift brought about by oversampling is described.
Reconfigurable Polyphase Filter Bank Architecture for Spectrum Sensing
- Suhaib A. Fahmy L. Doyle
- 2010
Computer Science, Engineering
A general architecture for implementation of filter banks on FPGAs is presented, exploiting heterogeneous resources, taking advantage of the fact that subband filters run at a reduced sample rate, and hence can share the same computational resources.
Multirate Signal Processing for Communication Systems
- F. Harris
- 2004
Engineering, Computer Science
This book offers the first systematic, clear, and intuitive introduction to multirate signal processing for working engineers and system designers.
Comparison of Wideband Channelisation Architectures
- J. Lillington
- 2003
Computer Science, Engineering
Comparisons between the competing techniques for real-time wideband channelisation including the pipelined FFT, Polyphase DFT's, multiple digital down-converters (DDC’s), the Pipelined Frequency Transform (PFT) and its derivative, the Tuneable PFT (TPFT) are made.
A polyphase filter for many-core architectures
- K. Adámek Jan Novotný W. Armour
- 2016
Computer Science, Engineering
Channelized Receiver with WOLA Filterbank
- Hong Wang Youxin Lu Xue-gang Wang
- 2006
Engineering
2006 CIE International Conference on Radar
Polyphase DFT filterbank is an efficient structure for channelized receivers, but its flexibility limited by the fixed relationship between decimating factor and channel number. In this paper, a...