(This page has a few highlights of chapter 4 of AL39-01, the processor manual for Multics).
Instruction Repertoire
Basic Operations
The 456 basic operations in the processor all require exactly one 36-bit machine word. They are categorized as follows:
181 Fixed-point binary arithmetic
85 Boolean operations
34 Floating-point binary arithmetic
36 Transfer of control
75 Pointer Register
17 Miscellaneous
28 Privileged
Extended Instruction Set (EIS) Operations
The 91 extended instruction set (EIS) operations are divided into 62 EIS single-word instructions and 29 EIS multiword instructions.
EIS Single-word Operations
The 62 EIS single-word instructions load, store, and perform special arithmetic on the address registers (ARn) used to access bit- and character-string operands, and safe-store decimal unit (DU) control information required to service a processor fault or interrupt. Like the basic operations, EIS single-word instructions require exactly one 36-bit machine word.
EIS Multiword Operations
The 29 EIS multiword instructions perform decimal arithmetic and bit- and character-string operations. They require three or four 36-bit machine words depending on individual operand descriptor requirements.
Instruction Word Formats
Basic and EIS Single-Word Instructions
Bits 0-17 - ADDRESS (many formats possible for the address)
Bits 18-27 - OPCODE
Bit 28 - I (Interrupt Inhibit)
Bit 29 - A (Indirect via pointer register flag)
Bits 30-35 - TAG (Instruction address modifier)
Indirect Words
Certain of the basic EIS single-word instructions permit indirection to be specified as part of address modification. When such indirection is specified, C(Y) (the resulting target address of the instruction - Ed.) is interpreted as an indirect word according to the following format:
Bits 0-17 - ADDRESS (many formats possible)
Bits 18-29 - TALLY (count field)
Bits 30-35 - TAG (several formats, depending on TAG of original instruction)
Fixed Point Arithmetic Instructions
Fixed-Point Data Movement Load
eaa Effective Address to A
eaq Effective Address to Q
eaxn Effective Address to Index Register n
lca Load Complement A
lcaq Load Complement AQ
lcq Load Complement Q
lcxn Load Complement Index Register n
lda Load A
ldac Load A and Clear
ldaq Load AQ
ldi Load Indicator
ldq Load Q
ldqc Load Q and Clear
ldxn Load Index Register n
lreg Load Registers
lxln Load Index Register n from Lower
sreg Store Registers
stba Store Bytes of A
stbq Store Bytes of Q
stc1 Store Instruction Counter Plus 1
stc2 Store Instruction Counter Plus 2
stca Store Characters of A
stcq Store Characters of Q
stcd Store Control Double
sti Store Indicator Register
stq Store Q
stt Store Time Register
stxn Store Index Register n
stz Store Zero
sxln Store Index Register n in Lower
Fixed-Point Data Movement Shift
alr A Left Rotate
als A Left Shift
arl A Right Logical
ars A Right Shift
llr Long Left Rotate
lls Long Left Shift
lrl Long Right Logical
lrs Long Right Shift
qlr Q Left Rotate
qls Q Left Shift
qrl Q Right Logical
qrs Q Right Shift
Fixed-Point Addition
ada Add to A
adaq Add to AQ
adl Add Low o AQ
adla Add Logical to A
adlaq Add Logical to AQ
adlq Add Logical to Q
adlxn Add Logical to Index Register n
adq Add to Q
adxn Add to Index Register n
aos Add One to Storage
asa Add Stored to A
asq Add Stored to Q
asxn Add Stored to Index Register n
awca Add with Carry to A
awcq Add with Carry to Q
Fixed-Point Subtraction
sba Subtract from A
sbaq Subtract from AQ
sbla Subtract Logical from A
sblaq Subtract Logical from AQ
sblq Subtract Logical from Q
sblxn Subtract Logical from Index Register n
sbq Subtract from Q
sbxn Subtract from Index Register n
ssa Subtract Stored from A
ssq Subtract Stored from Q
ssxn Subtract Stored from Index Register n
swca Subtract with Carry from A
swcq Subtract with Carry from Q
Fixed-Point Multiplication
mpf Multiply Fraction
mpy Multiply Integer
Fixed-Point Division
div Divide Integer
dvf Divide Fraction
Fixed-Point Negate
neg Negate A
negl Negate Long
Fixed-Point Comparison
cmg Compare Magnitude
cmk Compare Masked
cmpa Compare with A
cmpaq Compare with AQ
cmpq Compare with Q
cmpxn Compare with Index Register n
cwl Compare with Limits
Fixed-Point Miscellaneous
szn Set Zero and Negative Indicators
sznc Set Zero and Negative Indicators and Clear
Boolean Operations Instructions
Boolean And
ana AND to A
anaq AND to AQ
anq AND to Q
ansa AND to Storage A
ansq AND to Storage Q
ansxn AND to Storage Index Register n
anxn AND to Index Register n
Boolean Or
ora OR to A
oraq OR to AQ
orq OR to Q
orsa OR to Storage A
orsq OR to Storage Q
orsxn OR to Storage Index Register n
orxn OR to Index Register n
Boolean Exclusive Or
era EXCLUSIVE OR to A
eraq EXCLUSIVE OR to AQ
erq EXCLUSIVE OR to Q
ersa EXCLUSIVE OR to Storage A
ersq EXCLUSIVE OR to Storage Q
ersxn EXCLUSIVE OR to Storage Index Register n
erxn EXCLUSIVE OR to Index Register n
Boolean Comparative And
cana Comparative AND with A
canaq Comparative AND with AQ
canq Comparative AND with Q
canxn Comparative AND with Index Register n
Boolean Comparative Not
cnaa Comparative NOT with A
cnaaq Comparative NOT with AQ
cnaq Comparative NOT with Q
cnaxn Comparative NOT with Index Register n
Floating-Point Arithmetic Instructions
Floating-Point Data Movement Load
dfld Double-Precision Floating Load
fld Floating Load
dfst Double-Precision Floating Store
dfstr Double-Precision Floating Store Rounded
fst Floating Store
fstr Floating Store Rounded
Floating-Point Addition
dfad Double-Precision Floating Add
dufa Double-Precision Unnormalized Floating Add
fad Floating Add
ufa Unnormalized Floating Add
Floating-Point Subtraction
dfsb Double-Precision Floating Subtraction
dufs Double-Precision Unnormalized Floating Subtraction
fsb Floating Subtraction
ufs Unnormalized Floating Subtraction
Floating-Point Multiplication
dfmp Double-Precision Floating Multiply
dufm Double-Precision Unnormalized Floating Multiply
fmp Floating Multiply
ufm Unnormalized Floating Multiply
Floating-Point Division
dfdi Double-Precision Floating Divide Inverted
dfdv Double-Precision Floating Divide
fdi Floating Divide Inverted
fdv Floating Divide
Floating-Point Negate
fneg Floating Negate
Floating-Point Normalize
fno Floating Normalize
Floating-Point Round
dfrd Double-Precision Floating Round
frd Floating Round
Floating-Point Compare
dfcmg Double-Precision Floating Compare Magnitude
dfcmp Double-Precision Floating Compare
fcmg Floating Compare Magnitude
fcmp Floating Compare
Floating-Point Miscellaneous
ade Add to Exponent
fszn Floating Set Zero and Negative Indicators
lde Load Exponent
ste Store Exponent
Transfer Instructions
call6 Call (using PR6 and PR7)
ret Return
rtcd Return Control Double
teo Transfer on Exponent Overflow
teu Transfer on Exponent Underflow
tmi Transfer on Minus
tmoz Transfer on Minus or Zero
tnc Transfer on No Carry
tnz Transfer on Nonzero
tov Transfer on Overflow
tpl Transfer on Plus
tpnz Transfer on Plus and Nonzero
tra Transfer Unconditionally
trc Transfer on Carry
trtf Transfer on Truncation Indicator OFF
trtn Transfer on Truncation Indicator ON
tspn Transfer and Set Pointer Register n
tss Transfer and Set Slave
tsxn Transfer and Set Index Register n
ttf Transfer on Tally Runout Indicator OFF
ttn Transfer on Tally Runout Indicator ON
tze Transfer on Zero
Pointer Register Instructions
Pointer Register Data Movement Load
easpn Effective Address to Segment Number of Pointer Register n
epbpn Effective Pointer at Base to Pointer Register n
eppn Effective pointer to Pointer Register n
lpri Load Pointer Registers from ITS Pairs
lprpn Load Pointer Register n Packed
spbpn Store Segment Base Pointer of Pointer Register n
spri Store Pointer Registers as ITS Pairs
sprin Store Pointer Register n as ITS Pairs
sprpn Store Pointer Register n Packed
Pointer Register Address Arithmetic
adwpn Add Word Number of Pointer Register n
Pointer Register Miscellaneous
epaq Effective Pointer to AQ
Miscellaneous Instructions
Calendar Clock
rccl Read Calendar Clock
Derail
drl Derail
Execute
xec Execute
xed Execute Double
Master Mode Entry
mme Master Mode Entry
mme2 Master Mode Entry 2
mme3 Master Mode Entry 3
mme4 Master Mode Entry 4
No Operation
nop No Operation
puls1 Pulse One
puls2 Pulse Two
Repeat
rpd Repeat Double
rpl Repeat Link
rpt Repeat
Ring Alarm Register
sra Store Ring Alarm Register
Store Base Address Register
sbar Store Base Address Register
Translation
bcd Binary to Binary-Coded-Decimal
gtb Gray to Binary
Register Load
lbar Load Base Address Register
Privileged Instructions
Privileged - Register Load
lcpr Load Central Processor Register
ldbr Load Descriptor Segment Base Register
ldt Load Timer Register
lptp Load Page Table Pointers
lptr Load Page Table Registers
lra Load Ring Alarm Register
lsdp Load Segment Descriptor Pointers
lsdr Load Segment Descriptor Registers
rcu Restore Control Unit
Privileged - Register Store
scpr Store Central Processor Register
scu Store Control Unit
sdbr Store Descriptor Segment Base Register
sptp Store Page Table Pointers
sptr Store Page Table Registers
ssdp Store Segment Descriptor Pointers
ssdr Store Segment Descriptor Registers
Privileged - Clear Associative Memory
camp Clear Associative Memory Pages
cams Clear Associative Memory Segments
Privileged - Configuration and Status
rmcm Read Memory Controller Mask Register
rscr Read System Controller Register
rsw Read Switches
Privileged - System Control
cioc Connect I/O Channel
smcm Set Memory Controller Mask Register
smic Set Memory Controller Interrupt Cells
sscr Set System Controller Register
Privileged - Miscellaneous
absa Absolute Address to A-Register
dis Delay Until Interrupt Signal
Extended Instruction Set (EIS)
EIS - Address Register Load
asrn Alphanumeric Descriptor to Address Register n
larn Load Address Register n
lareg Load Address Registers
lpl Load Pointers and Lengths
narn Numeric Descriptor to Address Register n
EIS - Register Store
aran Address Register n to Alphanumeric Descriptor
arnn Address Register n to Numeric Descriptor
sarn Store Address Register n
sareg Store Address Registers
spl Store Pointers and Lengths
EIS - Address Register Special Arithmetic
a4bd Add 4-bit Displacement to Address Register
a6bd Add 6-bit Displacement to Address Register
a9bd Add 9-bit Displacement to Address Register
abd Add Bid Displacement to Address Register
awd Add Word Displacement to Address Register
s4bd Subtract 4-bit Displacement from Address Register
s6bd Subtract 6-bit Displacement from Address Register
s9bd Subtract 9-bit Displacement from Address Register
sbd Subtract bit Displacement from Address Register
swd Subtract Word Displacement from Address Register
EIS - Alphanumeric Compare
cmpc Compare Alphanumeric Character Strings
scd Scan Characters Double
scdr Scan Characters Double in Reverse
scm Scan with Mask
scmr Scan with Mask in Reverse
tct Test Character and Translate
tctr Test Character and Translate in Reverse
EIS - Alphanumeric Move
mlr Move Alphanumeric Left to Right
mrl Move Alphanumeric Right to Left
mve Move Alphanumeric Edited
mvt Move Alphanumeric with Translation
EIS - Numeric Compare
cpmn Compare Numeric
EIS - Numeric Move
mvn Move Numeric
mvne Move Numeric Edited
EIS - Bit String Combine
csl Combine Bit Strings Left
csr Combine Bit Strings Right
EIS - Bit String Compare
cmpb Compare Bit Strings
EIS - Bit Strings Set Indicators
sztl Set Zero and Truncation Indictors with Bit Strings Left
sztr Set Zero and Truncation Indictors with Bit Strings Right
EIS - Data Conversion
btd Binary to Decimal Convert
dtb Decimal to Binary Convert
EIS - Decimal Addition
ad2d Add Using Two Decimal Operands
ad3d Add Using Three Decimal Operands
EIS - Decimal Subtraction
sb2d Subtract Using Two Decimal Operands
sb3d Subtract Using Three Decimal Operands
EIS - Decimal Multiplication
mp2d Multiply Using Two Decimal Operands
mp3d Multiply Using Three Decimal Operands
EIS - Decimal Division
dv2d Divide Using Two Decimal Operands
dv3d Divide Using Three Decimal Operands
Micro Operations for Edit Instructions
(In the mve and mvne instructions, you can 'program' the instruction with a number of operations. Here are their titles. They are not operations, they are sub-operations of mve and mvne)
Micro Operations
cht Change Table (21)
enf End Floating Suppression (02)
ign Ignore Source Character (14)
insa Insert Asterisk on Suppression (11) (useful for printing checks from COBOL Ed.)
insb Insert Blank on Suppression (10)
insm Insert Table Entry One Multiple (01)
insn Insert On Negative (12)
insp Insert On Positive (13)
lte Load Table Entry (20)
mflc Move with Floating Currency Symbol Insertion (07)
mfls Move with Floating Sign Insertion (06)
mors Move and OR Sign (17)
mses Move and Set Sign (16)
mvc Move Source Characters (15)
mvza Move with Zero Suppression and Asterisk Replacement (05)
mvzb Move with Zero Suppression and Blank Replacement (04)
ses Set End Suppression (03)
Last modified: 10/14/00 by Ron Harvey