Write a delay subroutine program for SAP-II computer to introduce a time 1. delay of 1 millisec using only one register. Let the system frequency is 2 MHz.

0 0 0 W 0 0 0 0 0 1 1 1 Complete the truth table for the circuit below. It has four inputs (w, x, y, z) and two outputs (C, S). In a given row, outputs for both S, C should be correct to get any credit. w x y z 1 X 0 0 0 0 1 1 1 1 0 0 0 0 y 0 0 1 1 0 0 1 1 0 0 1 1 I1 DECODER Io 3 Z 0 1 0 1 0 1 0 1 0 1 0 1 2 MUX mui 3 Bo S FULL ADDER -S C

Develop a simple automated industrial temperature regulator system for operating the coolant relief valve in a high-temperature furnace. When the temperature exceeds the safety threshold value, this will set the sensor ON which is connected to the input port of a microcontroller. The relief valve itself is connected to the output of the microcontroller. The safety system should work as described below: 1. The temperature sensor is connected to Port B, bit 3 of the microcontroller 2. The relief valve is connected to Port A, bits 1 and 2 of the microcontroller 3. When the temperature in the furnace exceeds the threshold value, the sensor sets the input port B, bit 3 to ON. 4. When the sensor is ON, the microcontroller sends an appropriate output to Port A inorder to open the coolant relief valve. 5. As soon as the sensor goes to the OFF state, the microcontroller clears all the output port bits thus closing the relief valve. Q1. A flowchart can be used to describe the step-by-step plan...

Draw the Moore machine state diagram with minimal states for the digital alarm clock system(both of time set and alarm set)

Consider a circuit designed as follows: • one 1-bit register (like those discussed in class), with an attached clock • one not gate • wire A connects the register's ouput and the not's input • wire B connects the not's output and the register's input If we put a 1 onto wire B: A. wire A gets a 0 immediately B. wire A gets a 0 after the short delay it takes the gates in the register to finish work C. wire A gets a 0 after the next clock tick D. wire A gets a 1 immediately E. wire A gets a 1 after the short delay it takes the gates in the register to finish work O F. wire A gets a 1 after the next clock tick

5. Consider the following description of a finite-state machine. The single external input is X; the single output is Y. Design the sequential circuit using J-K flip-flops Present State Next State Input X 0 0 0 0 1 1 1 1 9.0. 00 01 10 11 00 01 10 1 1 99 10 01 11 10 11 00 00 01 Output Y 0 0 0 1 0 0 للطباعة والاستنساخ

Write VHDL code for this FSM. Add an asynchronous RESET, active High to the state diagram.

Assume we are writing a testbench for a sequential circuit that has three control inputs (cA, cB, cC) and a periodic clock (clk). If we define CLK_PERIOD as a localparameter with a value of 50 (nsec), write the testbench segment that would ensure all possible combinations of the control inputs were tested on a clock rising edge. This is can be done more elegantly if you define each time step in terms of the constant CLK_PERIOD. Your answer should include the statements that define clk, cA, cB, and cC over time. Hint: think of how you would show all combinations of three variables on a truth table and replicate that over time, where each combination is held over a timespan with a clock triggering edge.

Assume that an external clock signal is being fed into pin T0CKI (RA4). Write a C program touse Timer0 in 8-bit mode to count the pulses and display the state of the TMR0L count onPORTB. Start the count at 0x00 and stop the count at 0xFF+1. Use the MPLAB simulatorto verify the proper operation of the program

The circuit below is a 4-bit shifter with 2 control inputs s1 and s0, 4 data inputs 13, 12, 11, and 10, and 4 data outputs Q3, Q2, Q1, and Q0. If the input 13 12 11 10 =わ 1101, what is the final output when s1 s0 = 01 and then 11 next clock cycle ? 13 12 I1 IO s1 s0 Q3 Q2 Q1 QO 0000 0010 0110 O 1010

Design a finite state machine (FSM) with one input A and two outputs S and L. The FSM should detect whether a short or a long pulse appears on input A and assert output S in case of a short pulse and assert output L in case of a long pulse. A short pulse is defined as a pulse that lasts up to a single state duration and a long pulse is defined as a pulse that lasts for more than one state transition. Draw the algorithmic state machine (ASM) chart of your FSM design.

Realize a Moore machine with one external input S and a 3-bit output 020100 representing a 3-bit binary number. The circuit outputs indefinitely either the sequence of values 1, 3, 5, 1, 3, 5, 1, 3, ... when S=1, or the sequence of values 1, 5, 3, 1, 5, 3, 1, 5, ... when S=0. Use a binary state encoding with exactly 2 D flip-flops. You can decide when transitions between the sequences occur, the new sequence can start at any digit. On reset the system starts by showing the number 3. i) write the state diagram; include the transition conditions and the output value; ii) write the truth table for the next state; iii) write the truth table for the output;

Implement Lamport’s logical clocks with three process p1, p2, p3 where each clock duration at 3, 5, and 6 respectively