In this problem you have to design a 3-bit arithmetic unit (AU) which executes the micro- operations described in the following table. The AU takes its operands from two 3-bit registers A=A2A1A0 and B=B2B1B0, and returns an output F = F2F1F0. The micro-operation to be executed is specified by the code bits x, y and z. Assume that the contents of A and B are signed numbers in 2's complement representation. Draw a detailed logic diagram of the circuit using 1-bit full adders and any digital components of your choice (encoders, decoders, multiplexers, gates, etc.) (Note: X' is the 1's complement of X) z=0 F-A (2's complement of A) F=A-B (subtraction) - x y z=1 00 FA 1 01 F = A-B-1 10 11 F= A÷2+1 (half incremented) F=A+B+1 (add with carry) = F= A÷2 (half division by 2) F = A + B (add) Bonus Replace division by 2 in the 3rd row of the above table (F = A÷2) with multiplication by 3, (i.e., F = 3 x A, if z=1, and F = 3 x A + 1 if z=0) and provide the logic diagram of the new circuit.

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