Systems Architecture
Systems Architecture
7th Edition
ISBN: 9781305080195
Author: Stephen D. Burd
Publisher: Cengage Learning
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[画像:Design a digital circuit with the minimum number of gates with the 4-bit input A = a3a2a1a0 and the 4-bit output B = b3b2b1bo. Your design must be according to the following specifications - If A is 0, then B must take a don't care value. - If A is divisible by both 3 and 5, B must take a don't care value. - If A is divisible by 3 but not divisible by 5, then B = A ÷ 3. - If A is divisible by 5 but not divisible by 3, then B = A ÷ 5. - If A is not divisible by either 3 or 5, then B = A ×ばつ 3. If this multiplication result exceeds the maximum allowed range value, then B must be replaced with a don't care value. a. Plot a truth table, K-maps, and derive the corresponding logic diagram. (Assume variables and their complements are available). Your diagram must be a single circuit producing all output bits of B. b. Redraw the logic diagram of the circuit using only NAND gates. (Assume variables and their complements are available) c. Redraw the logic diagram of the circuit using only NOR gates. (Assume variables and their complements are available)]
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Transcribed Image Text:Design a digital circuit with the minimum number of gates with the 4-bit input A = a3a2a1a0 and the 4-bit output B = b3b2b1bo. Your design must be according to the following specifications - If A is 0, then B must take a don't care value. - If A is divisible by both 3 and 5, B must take a don't care value. - If A is divisible by 3 but not divisible by 5, then B = A ÷ 3. - If A is divisible by 5 but not divisible by 3, then B = A ÷ 5. - If A is not divisible by either 3 or 5, then B = A ×ばつ 3. If this multiplication result exceeds the maximum allowed range value, then B must be replaced with a don't care value. a. Plot a truth table, K-maps, and derive the corresponding logic diagram. (Assume variables and their complements are available). Your diagram must be a single circuit producing all output bits of B. b. Redraw the logic diagram of the circuit using only NAND gates. (Assume variables and their complements are available) c. Redraw the logic diagram of the circuit using only NOR gates. (Assume variables and their complements are available)
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