Briefly describe the following: a. Configurable logic blocks b. "Synthesis" process in FPGA c. Timing diagrams d. Differentiate between reg and wire in Verilog e. How to add delay in Verilog testbench. Give a simple example

D b X y D Q pa2 C CLK clk a 1 2 3 4 5 6 7 8 b X с Y

Vsig Rsig www Rin RB1 RB2 Vcc If Vsig = 20 mVp value of Vout. Rc HH Rout RE RL + The common-emitter discrete amplifier shown has the following values: RB1 = Vout = 500 kQ, RB2 = 100 kQ, Rc = 5 k2, RE 200 2,ドル Rsig = 1 kN, R1 = 10 k§ and Vcc= 22 V. Assume VBE = 0.7 V and B = 90. Also assume that the capacitors are shorts for ac. The bias circuit has been analyzed and Ic = 2.63 mA, Rin = 0.856 k and Rout = Rc. peak, determine the peak

I don’t understand this question. Professor told me to show my work if possible. Thank you in advance.

A1 A2 GND GND 3 Junction box GND GND 4.

can you do question iii please?