A processor has an 30-bit physical address space (A memory address is 30-bit). It also has a physically addressed, 8-way set associative cache. If the size of the entire cache is 64 KB, and the block size is 4Byte How many sets (i.e. lines) exist in this cache? How many bits are used to address each cache line?(index bits?) How many bits are stored in the tag area?

For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache. Tag Index Offset 63-9 8-5 |4-0 Beginning from power on, the following byte-addressed cache references are recorded. |Нех 00 04 10 84 E8 A0 | 400||1E 8C C1C B4 884 (A) For each reference, list (i) its tag, index, and offset, (ii) whether it is a hit or a miss, and (iii) which bytes were replaced (if any). (B) What is the hit ratio? (C) List the final state of the cache, with each valid entry represented as a record of . For example,

Suppose a byte-addressable computer using set associative cache has 224 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?

Suppose a computer using direct-mapped cache has 232 (that's 232)232) bytes of byte-addressable main memory, and a cache size of 512 bytes, and each cache block contains 64 bytes. How many blocks of main memory are there? What is the format of a memory address as seen by cache, i.e. what are the sizes of the tag, block, and offset fields? To which cache block will the memory address 0x13A4498A map?

A memory system has 4 KB byte-addressable main memory and a direct-mapped cache that consists of 8 blocks with 16 bytes per block. The following shows the main memory address format that allows us to map addresses from main memory to cache. Note: 12 bit address, 4 bit offset, 3 bit $block, and 5 bit tag Assume the cache directory shown below:

Suppose a computer using direct mapped cache has 236 bytes of byte-addressable main memory and a cache size of 1024 bytes, and each cache block contains 64 bytes. ⦁ How many blocks of main memory are there? ⦁ What is the format of a memory address as seen by cache, i.e., what are the sizes of the tag, block, and offset fields? ⦁ To which cache block will the memory address 0x13A4576B map?

Suppose a computer using fully associative cache has 216 bytes of byte-addressable main memory and a cache of 64 blocks, where each cache block contains 32 bytes.Q.) What is the format of a memory address as seen by the cache; that is, what are the sizes of the tag and offset fields?

Suppose a byte-addressable computer using set-associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes.Q.) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?

Given a MIPS processor with a direct-mapped data cache. On this processor the following code is running: sum = 0; for (i=0; i<4; i++) sum = sum + A[i) + A[i+2]; 'A' is an array of (32-bit) integers, word-aligned in memory. All other variables used in this program are already located in registers. What is the data cache hit-rate (in number of percents) for this program, assuming that the cache has a block size of 1 word? Answer:

In a certain computer, the virtual addresses are 32 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 16 kB and the word size is 2 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 64 valid entries. Hit ratio of TLB is 100% then maximum number of distinct virtual addresses that can be translated is K.

Assume the address format for a fully-associative cache is as follows: 6 bits 2 bits Tag Offset 8 bits Given the cache directory is as shown in the diagram below, indicate whether the memory reference Ox5E results in a cache hits or a miss. Tag valid Block 000 110110 001 000001 010 000010 011 000101 100 001000 1 101 100010 110 010111 111 110110 O Hit O Miss

A cache is organized as a 4 way set associative cache Each set's cache line consists of 4 words (meaning there are 16 bytes per line, for each set of the cache). Each set individually has one Valid bit, and one Dirty bit, for each line. The tag field of this cache is 8 bits wide. The address is 32 bits wide. Question 1c) What is the cache size? (Meaning the number of kilobytes of data being stored in this cache, ignoring the tag, dirty, and valid bits) Question 1d) If this same sized cache (meaning the number of kilobytes of the data part from the question 1c above) are instead organized as a direct mapped cache, what is the total number of 'memory bitcells' needed to design this cache instead (meaning how many bitcells including the tag, dirty, and valid bits? (Assume that the number of cache lines are not changing and that all the bytes of all four sets are now coalesced into one set, thus making it a direct mapped cache)

Suppose a computer using fully associative cache has 220220 words of main memory and a cache of 128 blocks, where each cache block contains 16 words. (a) How many blocks of main memory are there? (b) What is the format of a memory address as seen by the cache, that is, what are the sizes of the tag and word fields? (c) To which cache block will the memory reference 01D872_{16}01D872_{16} map?