2. 2. Suppose a computer using direct-mapped cache has 232 bytes of byte-addressable main memory and a cache of 1024 blocks, where each cache block contains 32 bytes. 1. a) How many blocks of main memory are there? 2. b) What is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, block, and offset fields? 3. c) To which cache block will the memory address ox000063FA map?

operating system

5. How many bits are required to address a 4M X 16 main memory if a) main memory is byte addressable? b) main memory is word addressable? 6. How many bits are required to address a 1M X 8 main memory if a) main memory is byte addressable? b) main memory is word addressable?

8.9. The IBM System/370 architecture uses a two-level memory structure and refers to the two levels as segments and pages, although the segmentation approach lacks many of the features described earlier in this chapter. For the basic 370 architecture, the page size may be either 2 Kbytes or 4 Kbytes, and the segment size is fixed at either 64 Kbytes or 1 Mbyte. For the 370/XA and 370/ESA architectures, the page size is 4 Kbytes and the segment size is 1 Mbyte. Which advantages of segmentation does this scheme lack? What is the benefit of segmentation for the 370?

QUESTION 9 1. If a given memory address for a byte addressable machine is found in a cache that uses a 128 byte cache line size, the least significant 8 bits in the memory address will be used to select the byte(s) in the cache line to work with. True False QUESTION 10 1. SRAM memory is used predominately in: C SRAM memory is used predominately in: C motherboard main memory C BIOS PROM memory C SD card memory devices C CPU on-chip cache memory

4. Assume 32 bit memory addresses, which are byte addresses. You have a direct-mapped cache with a block size of 8 bytes, and a size of 128 blocks. How many bits will the index, block offset, and tag be? How many total bits are required for the cache, including the data?

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QUESTION 2 Suppose a computer using direct mapped cache is using 216 (64K) bytes of byte-addressable main memory, and a cache size of 4096 bytes, where each cache block contains 256 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by cache, i.e. what are the length of the tag, block, and offset fields? c) Given memory address 2B9D (in hexadecimal format), which block in the cache will be searched? (What is that block's id?)

P2

3. The table below represents a stack stored in a contiguous block of memory cells (as discussed in the text). If the base of the stack is at address 0x10 and the stack pointer contains the value 0x12, what value is retrieved by a pop instruction? What value is in the stack pointer after the pop operation? Address 0x10 0x11 0x12 0x13 0x14 Contents 'F' 'C' 'A' 'B' 'E'

Question 9

5. The ending address of a memory of size 1KB is 33FFH, then what is the starting address of the memory.

Before we can store (save) or retrieve (load) data in and out of the main memory, we need to provide the memory address to the memory control unit. This address uniquely identifies one single location (word or record) of the memory. Suppose this address is placed in Memory Address Register (MAR) prior to each memory access. What is the size of MAR for a 4GB RAM? (RAM is byte- addressable and each word is 2 bytes). Show all the work.