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Component Nodes

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Component Nodes#

SignalNode#

classsystemrdl.node.SignalNode(inst:Component, env:RDLEnvironment, parent:Node |None)#

Inherits: VectorNode

Represents an RDL signal.

get_property(prop_name:Literal['signalwidth'], *, default:T) → int|T#

get_property(prop_name:Literal['signalwidth'], **kwargs:Any) → int

get_property(prop_name:Literal['sync'], *, default:T) → bool|T

get_property(prop_name:Literal['sync'], **kwargs:Any) → bool

get_property(prop_name:Literal['async'], *, default:T) → bool|T

get_property(prop_name:Literal['async'], **kwargs:Any) → bool

get_property(prop_name:Literal['cpuif_reset'], *, default:T) → bool|T

get_property(prop_name:Literal['cpuif_reset'], **kwargs:Any) → bool

get_property(prop_name:Literal['field_reset'], *, default:T) → bool|T

get_property(prop_name:Literal['field_reset'], **kwargs:Any) → bool

get_property(prop_name:Literal['activelow'], *, default:T) → bool|T

get_property(prop_name:Literal['activelow'], **kwargs:Any) → bool

get_property(prop_name:Literal['activehigh'], *, default:T) → bool|T

get_property(prop_name:Literal['activehigh'], **kwargs:Any) → bool

get_property(prop_name:Literal['name'], *, default:T) → str|T

get_property(prop_name:Literal['name'], **kwargs:Any) → str

get_property(prop_name:Literal['desc'], *, default:T) → str|None|T

get_property(prop_name:Literal['desc'], **kwargs:Any) → str|None

get_property(prop_name:Literal['ispresent'], *, default:T) → bool|T

get_property(prop_name:Literal['ispresent'], **kwargs:Any) → bool

get_property(prop_name:str, *, default:T) → Any|T

get_property(prop_name:str, **kwargs:Any) → Any

Gets the SystemRDL component property

If a property was not explicitly set in the RDL source, its default value is derived. In some cases, a default value is implied according to other property values.

Properties values that are a reference to a component instance are converted to a Node overlay object.

Parameters:

• prop_name (str) – SystemRDL property name

• default – Override built-in default value of property. If the property was not explicitly set, return this value rather than the property’s intrinsic default value.

Raises:

LookupError – If prop_name is invalid

inst:Signal#

Reference to Component data object.

Deprecated since version 1.30: Querying the internal Component objects is no longer recommended.

Equivalents for most concepts have been made available as direct methods or properties of Node objects. It is strongly recommended to use these instead to prevent compatibility issues.

parent:Node #

Reference to parent Node

FieldNode#

classsystemrdl.node.FieldNode(inst:Component, env:RDLEnvironment, parent:Node |None)#

Inherits: VectorNode

Represents an RDL field

propertyalias_primary:FieldNode #

Returns the FieldNode that is associated with this alias’s primary register.

Raises ValueError if this field is not an alias

Added in version 1.23.

aliases(skip_not_present:bool=True) → List[FieldNode ]#

Returns a list of all the fields that are aliases of this primary field.

Parameters:

skip_not_present (bool) – If True, skips aliases whose ‘ispresent’ property is set to False

Added in version 1.23.

Changed in version 1.29: Returns list instead of generator

get_global_type_name(separator:str='__') → str|None#

Returns a globally scoped type name that can be used to uniquely identify this node’s type.

If scope or type name information is not available due to the node being imported from a non-RDL source, this will return None.

Added in version 1.27.0.

get_property(prop_name:Literal['dontcompare'], *, default:T) → int|bool|T#

get_property(prop_name:Literal['dontcompare'], **kwargs:Any) → int|bool

get_property(prop_name:Literal['donttest'], *, default:T) → int|bool|T

get_property(prop_name:Literal['donttest'], **kwargs:Any) → int|bool

get_property(prop_name:Literal['hdl_path_slice'], *, default:T) → List[str]|None|T

get_property(prop_name:Literal['hdl_path_slice'], **kwargs:Any) → List[str]|None

get_property(prop_name:Literal['hdl_path_gate_slice'], *, default:T) → List[str]|None|T

get_property(prop_name:Literal['hdl_path_gate_slice'], **kwargs:Any) → List[str]|None

get_property(prop_name:Literal['hw'], *, default:T) → AccessType |T

get_property(prop_name:Literal['hw'], **kwargs:Any) → AccessType

get_property(prop_name:Literal['sw'], *, default:T) → AccessType |T

get_property(prop_name:Literal['sw'], **kwargs:Any) → AccessType

get_property(prop_name:Literal['next'], *, default:T) → FieldNode |SignalNode |PropertyReference |None|T

get_property(prop_name:Literal['next'], **kwargs:Any) → FieldNode |SignalNode |PropertyReference |None

get_property(prop_name:Literal['reset'], *, default:T) → int|FieldNode |SignalNode |PropertyReference |None|T

get_property(prop_name:Literal['reset'], **kwargs:Any) → int|FieldNode |SignalNode |PropertyReference |None

get_property(prop_name:Literal['resetsignal'], *, default:T) → SignalNode |None|T

get_property(prop_name:Literal['resetsignal'], **kwargs:Any) → SignalNode |None

get_property(prop_name:Literal['rclr'], *, default:T) → bool|T

get_property(prop_name:Literal['rclr'], **kwargs:Any) → bool

get_property(prop_name:Literal['rset'], *, default:T) → bool|T

get_property(prop_name:Literal['rset'], **kwargs:Any) → bool

get_property(prop_name:Literal['onread'], *, default:T) → OnReadType |None|T

get_property(prop_name:Literal['onread'], **kwargs:Any) → OnReadType |None

get_property(prop_name:Literal['woclr'], *, default:T) → bool|T

get_property(prop_name:Literal['woclr'], **kwargs:Any) → bool

get_property(prop_name:Literal['woset'], *, default:T) → bool|T

get_property(prop_name:Literal['woset'], **kwargs:Any) → bool

get_property(prop_name:Literal['onwrite'], *, default:T) → OnWriteType |None|T

get_property(prop_name:Literal['onwrite'], **kwargs:Any) → OnWriteType |None

get_property(prop_name:Literal['swwe'], *, default:T) → bool|SignalNode |FieldNode |PropertyReference |T

get_property(prop_name:Literal['swwe'], **kwargs:Any) → bool|SignalNode |FieldNode |PropertyReference

get_property(prop_name:Literal['swwel'], *, default:T) → bool|SignalNode |FieldNode |PropertyReference |T

get_property(prop_name:Literal['swwel'], **kwargs:Any) → bool|SignalNode |FieldNode |PropertyReference

get_property(prop_name:Literal['swmod'], *, default:T) → bool|T

get_property(prop_name:Literal['swmod'], **kwargs:Any) → bool

get_property(prop_name:Literal['swacc'], *, default:T) → bool|T

get_property(prop_name:Literal['swacc'], **kwargs:Any) → bool

get_property(prop_name:Literal['singlepulse'], *, default:T) → bool|T

get_property(prop_name:Literal['singlepulse'], **kwargs:Any) → bool

get_property(prop_name:Literal['we'], *, default:T) → bool|SignalNode |FieldNode |PropertyReference |T

get_property(prop_name:Literal['we'], **kwargs:Any) → bool|SignalNode |FieldNode |PropertyReference

get_property(prop_name:Literal['wel'], *, default:T) → bool|SignalNode |FieldNode |PropertyReference |T

get_property(prop_name:Literal['wel'], **kwargs:Any) → bool|SignalNode |FieldNode |PropertyReference

get_property(prop_name:Literal['anded'], *, default:T) → bool|T

get_property(prop_name:Literal['anded'], **kwargs:Any) → bool

get_property(prop_name:Literal['ored'], *, default:T) → bool|T

get_property(prop_name:Literal['ored'], **kwargs:Any) → bool

get_property(prop_name:Literal['xored'], *, default:T) → bool|T

get_property(prop_name:Literal['xored'], **kwargs:Any) → bool

get_property(prop_name:Literal['fieldwidth'], *, default:T) → int|T

get_property(prop_name:Literal['fieldwidth'], **kwargs:Any) → int

get_property(prop_name:Literal['hwclr'], *, default:T) → bool|SignalNode |FieldNode |PropertyReference |T

get_property(prop_name:Literal['hwclr'], **kwargs:Any) → bool|SignalNode |FieldNode |PropertyReference

get_property(prop_name:Literal['hwset'], *, default:T) → bool|SignalNode |FieldNode |PropertyReference |T

get_property(prop_name:Literal['hwset'], **kwargs:Any) → bool|SignalNode |FieldNode |PropertyReference

get_property(prop_name:Literal['hwenable'], *, default:T) → FieldNode |SignalNode |PropertyReference |None|T

get_property(prop_name:Literal['hwenable'], **kwargs:Any) → FieldNode |SignalNode |PropertyReference |None

get_property(prop_name:Literal['hwmask'], *, default:T) → FieldNode |SignalNode |PropertyReference |None|T

get_property(prop_name:Literal['hwmask'], **kwargs:Any) → FieldNode |SignalNode |PropertyReference |None

get_property(prop_name:Literal['counter'], *, default:T) → bool|T

get_property(prop_name:Literal['counter'], **kwargs:Any) → bool

get_property(prop_name:Literal['threshold'], *, default:T) → int|bool|SignalNode |FieldNode |PropertyReference |T

get_property(prop_name:Literal['threshold'], **kwargs:Any) → int|bool|SignalNode |FieldNode |PropertyReference

get_property(prop_name:Literal['incrthreshold'], *, default:T) → int|bool|SignalNode |FieldNode |PropertyReference |T

get_property(prop_name:Literal['incrthreshold'], **kwargs:Any) → int|bool|SignalNode |FieldNode |PropertyReference

get_property(prop_name:Literal['saturate'], *, default:T) → int|bool|SignalNode |FieldNode |PropertyReference |T

get_property(prop_name:Literal['saturate'], **kwargs:Any) → int|bool|SignalNode |FieldNode |PropertyReference

get_property(prop_name:Literal['incrsaturate'], *, default:T) → int|bool|SignalNode |FieldNode |PropertyReference |T

get_property(prop_name:Literal['incrsaturate'], **kwargs:Any) → int|bool|SignalNode |FieldNode |PropertyReference

get_property(prop_name:Literal['overflow'], *, default:T) → bool|T

get_property(prop_name:Literal['overflow'], **kwargs:Any) → bool

get_property(prop_name:Literal['underflow'], *, default:T) → bool|T

get_property(prop_name:Literal['underflow'], **kwargs:Any) → bool

get_property(prop_name:Literal['incr'], *, default:T) → FieldNode |SignalNode |PropertyReference |None|T

get_property(prop_name:Literal['incr'], **kwargs:Any) → FieldNode |SignalNode |PropertyReference |None

get_property(prop_name:Literal['incrvalue'], *, default:T) → int|FieldNode |SignalNode |PropertyReference |None|T

get_property(prop_name:Literal['incrvalue'], **kwargs:Any) → int|FieldNode |SignalNode |PropertyReference |None

get_property(prop_name:Literal['incrwidth'], *, default:T) → int|None|T

get_property(prop_name:Literal['incrwidth'], **kwargs:Any) → int|None

get_property(prop_name:Literal['decrvalue'], *, default:T) → int|FieldNode |SignalNode |PropertyReference |None|T

get_property(prop_name:Literal['decrvalue'], **kwargs:Any) → int|FieldNode |SignalNode |PropertyReference |None

get_property(prop_name:Literal['decr'], *, default:T) → FieldNode |SignalNode |PropertyReference |None|T

get_property(prop_name:Literal['decr'], **kwargs:Any) → FieldNode |SignalNode |PropertyReference |None

get_property(prop_name:Literal['decrwidth'], *, default:T) → int|None|T

get_property(prop_name:Literal['decrwidth'], **kwargs:Any) → int|None

get_property(prop_name:Literal['decrsaturate'], *, default:T) → int|bool|SignalNode |FieldNode |PropertyReference |T

get_property(prop_name:Literal['decrsaturate'], **kwargs:Any) → int|bool|SignalNode |FieldNode |PropertyReference

get_property(prop_name:Literal['decrthreshold'], *, default:T) → int|bool|SignalNode |FieldNode |PropertyReference |T

get_property(prop_name:Literal['decrthreshold'], **kwargs:Any) → int|bool|SignalNode |FieldNode |PropertyReference

get_property(prop_name:Literal['intr'], *, default:T) → bool|T

get_property(prop_name:Literal['intr'], **kwargs:Any) → bool

get_property(prop_name:Literal['intr type'], *, default:T) → InterruptType |None|T

get_property(prop_name:Literal['intr type'], **kwargs:Any) → InterruptType |None

get_property(prop_name:Literal['enable'], *, default:T) → FieldNode |SignalNode |PropertyReference |None|T

get_property(prop_name:Literal['enable'], **kwargs:Any) → FieldNode |SignalNode |PropertyReference |None

get_property(prop_name:Literal['mask'], *, default:T) → FieldNode |SignalNode |PropertyReference |None|T

get_property(prop_name:Literal['mask'], **kwargs:Any) → FieldNode |SignalNode |PropertyReference |None

get_property(prop_name:Literal['haltenable'], *, default:T) → FieldNode |SignalNode |PropertyReference |None|T

get_property(prop_name:Literal['haltenable'], **kwargs:Any) → FieldNode |SignalNode |PropertyReference |None

get_property(prop_name:Literal['haltmask'], *, default:T) → FieldNode |SignalNode |PropertyReference |None|T

get_property(prop_name:Literal['haltmask'], **kwargs:Any) → FieldNode |SignalNode |PropertyReference |None

get_property(prop_name:Literal['sticky'], *, default:T) → bool|T

get_property(prop_name:Literal['sticky'], **kwargs:Any) → bool

get_property(prop_name:Literal['stickybit'], *, default:T) → bool|T

get_property(prop_name:Literal['stickybit'], **kwargs:Any) → bool

get_property(prop_name:Literal['encode'], *, default:T) → Type[UserEnum ]|None|T

get_property(prop_name:Literal['encode'], **kwargs:Any) → Type[UserEnum ]|None

get_property(prop_name:Literal['precedence'], *, default:T) → PrecedenceType |T

get_property(prop_name:Literal['precedence'], **kwargs:Any) → PrecedenceType

get_property(prop_name:Literal['paritycheck'], *, default:T) → bool|T

get_property(prop_name:Literal['paritycheck'], **kwargs:Any) → bool

get_property(prop_name:Literal['name'], *, default:T) → str|T

get_property(prop_name:Literal['name'], **kwargs:Any) → str

get_property(prop_name:Literal['desc'], *, default:T) → str|None|T

get_property(prop_name:Literal['desc'], **kwargs:Any) → str|None

get_property(prop_name:Literal['ispresent'], *, default:T) → bool|T

get_property(prop_name:Literal['ispresent'], **kwargs:Any) → bool

get_property(prop_name:str, *, default:T) → Any|T

get_property(prop_name:str, **kwargs:Any) → Any

Gets the SystemRDL component property

If a property was not explicitly set in the RDL source, its default value is derived. In some cases, a default value is implied according to other property values.

Properties values that are a reference to a component instance are converted to a Node overlay object.

Parameters:

• prop_name (str) – SystemRDL property name

• default – Override built-in default value of property. If the property was not explicitly set, return this value rather than the property’s intrinsic default value.

Raises:

LookupError – If prop_name is invalid

propertyhas_aliases:bool#

Returns True if this field has aliases

Added in version 1.23.

propertyimplements_storage:bool#

True if combination of field access properties imply that the field implements a storage element.

Changed in version 1.22: Counter, interrupt, stickybit, and sticky fields always implement storage, regardless of sw/hw access.

Changed in version 1.23: Alias fields never implement storage. A primary field may inherit a storage element depending on the access modes of aliases that augment access to it.

Changed in version 1.30: All variants of software-writable access now imply a storage element.

All hardware-writable fields that are qualified by we or wel imply storage.

inst:Field#

Reference to Component data object.

Deprecated since version 1.30: Querying the internal Component objects is no longer recommended.

Equivalents for most concepts have been made available as direct methods or properties of Node objects. It is strongly recommended to use these instead to prevent compatibility issues.

propertyis_alias:bool#

Indicates whether this field is an alias (is contained inside an alias register)

Added in version 1.23.

propertyis_down_counter:bool#

Denotes whether this field is a counter and the property assignments imply it has down-counting functionality.

Added in version 1.21.

propertyis_hw_readable:bool#

Field is readable by hardware

propertyis_hw_writable:bool#

Field is writable by hardware

propertyis_sw_readable:bool#

Field is readable by software

propertyis_sw_writable:bool#

Field is writable by software

propertyis_up_counter:bool#

Denotes whether this field is a counter and the property assignments imply it has up-counting functionality.

Added in version 1.21.

propertyis_virtual:bool#

Determines if this node represents a virtual field (child of a virtual register)

propertyis_volatile:bool#

True if combination of field access properties result in a field that should be interpreted as volatile. (Any hardware-writable field is inherently volatile)

parent:RegNode #

Reference to parent Node

RegNode#

classsystemrdl.node.RegNode(inst:AddressableComponent, env:RDLEnvironment, parent:Node |None)#

Inherits: AddressableNode

Represents an RDL reg

propertyalias_primary:RegNode #

Returns the RegNode of this alias’s primary register.

Raises ValueError if this register is not an alias

Added in version 1.23.

aliases(skip_not_present:bool=True) → List[RegNode ]#

Returns a listof all the registers that are aliases of this primary register

Parameters:

skip_not_present (bool) – If True, skips aliases whose ‘ispresent’ property is set to False

Added in version 1.23.

Changed in version 1.29: Returns list instead of generator

fields(skip_not_present:bool=True, include_gaps:Literal[False]=False) → Sequence[FieldNode ]#

fields(skip_not_present:bool, include_gaps:Literal[True]) → Sequence[FieldNode |Tuple[int,int]]

fields(skip_not_present:bool=True, *, include_gaps:Literal[True]) → Sequence[FieldNode |Tuple[int,int]]

fields(skip_not_present:bool=True, include_gaps:bool=False) → Sequence[FieldNode |Tuple[int,int]]

Returns a list of all fields of this register.

Parameters:

• skip_not_present (bool) – If True, skips children whose ‘ispresent’ property is set to False

• include_gaps (bool) – If True, returned list also includes information about gaps between fields. Gaps are represented as tuples in the form of: (high, low)

Returns:

All fields in this component

Return type:

FieldNode

Changed in version 1.29: Returns list instead of generator.

Added include_gaps argument

get_property(prop_name:Literal['dontcompare'], *, default:T) → bool|T#

get_property(prop_name:Literal['dontcompare'], **kwargs:Any) → bool

get_property(prop_name:Literal['donttest'], *, default:T) → bool|T

get_property(prop_name:Literal['donttest'], **kwargs:Any) → bool

get_property(prop_name:Literal['errextbus'], *, default:T) → bool|T

get_property(prop_name:Literal['errextbus'], **kwargs:Any) → bool

get_property(prop_name:Literal['hdl_path'], *, default:T) → str|None|T

get_property(prop_name:Literal['hdl_path'], **kwargs:Any) → str|None

get_property(prop_name:Literal['hdl_path_gate'], *, default:T) → str|None|T

get_property(prop_name:Literal['hdl_path_gate'], **kwargs:Any) → str|None

get_property(prop_name:Literal['regwidth'], *, default:T) → int|T

get_property(prop_name:Literal['regwidth'], **kwargs:Any) → int

get_property(prop_name:Literal['accesswidth'], *, default:T) → int|T

get_property(prop_name:Literal['accesswidth'], **kwargs:Any) → int

get_property(prop_name:Literal['shared'], *, default:T) → bool|T

get_property(prop_name:Literal['shared'], **kwargs:Any) → bool

get_property(prop_name:Literal['name'], *, default:T) → str|T

get_property(prop_name:Literal['name'], **kwargs:Any) → str

get_property(prop_name:Literal['desc'], *, default:T) → str|None|T

get_property(prop_name:Literal['desc'], **kwargs:Any) → str|None

get_property(prop_name:Literal['ispresent'], *, default:T) → bool|T

get_property(prop_name:Literal['ispresent'], **kwargs:Any) → bool

get_property(prop_name:str, *, default:T) → Any|T

get_property(prop_name:str, **kwargs:Any) → Any

Gets the SystemRDL component property

If a property was not explicitly set in the RDL source, its default value is derived. In some cases, a default value is implied according to other property values.

Properties values that are a reference to a component instance are converted to a Node overlay object.

Parameters:

• prop_name (str) – SystemRDL property name

• default – Override built-in default value of property. If the property was not explicitly set, return this value rather than the property’s intrinsic default value.

Raises:

LookupError – If prop_name is invalid

propertyhas_aliases:bool#

Returns True if this register has aliases

Added in version 1.23.

propertyhas_hw_readable:bool#

Register contains one or more present fields readable by hardware

propertyhas_hw_writable:bool#

Register contains one or more present fields writable by hardware

propertyhas_sw_readable:bool#

Register contains one or more present fields readable by software

propertyhas_sw_writable:bool#

Register contains one or more present fields writable by software

inst:Reg#

Reference to Component data object.

Deprecated since version 1.30: Querying the internal Component objects is no longer recommended.

Equivalents for most concepts have been made available as direct methods or properties of Node objects. It is strongly recommended to use these instead to prevent compatibility issues.

propertyis_alias:bool#

Indicates whether this register is an alias.

Added in version 1.23.

propertyis_halt_reg:bool#

Register contains one or more interrupt fields that use haltenable or haltmask and therefore produces a halt output signal.

Added in version 1.22.

propertyis_interrupt_reg:bool#

Register contains one or more interrupt fields and therefore produces an interrupt output signal.

Added in version 1.22.

propertyis_msb0_order:bool#

If true, fields are arranged in msb0 order.

Added in version 1.30.

propertyis_virtual:bool#

True if this node represents a virtual register. (child of a mem component)

parent:AddrmapNode |RegNode |MemNode #

Reference to parent Node

propertysize:int#

Determine the size (in bytes) of this node.

If an array, returns the size of a single element

RegfileNode#

classsystemrdl.node.RegfileNode(inst:AddressableComponent, env:RDLEnvironment, parent:Node |None)#

Inherits: AddressableNode

Represents an RDL regfile

get_property(prop_name:Literal['dontcompare'], *, default:T) → bool|T#

get_property(prop_name:Literal['dontcompare'], **kwargs:Any) → bool

get_property(prop_name:Literal['donttest'], *, default:T) → bool|T

get_property(prop_name:Literal['donttest'], **kwargs:Any) → bool

get_property(prop_name:Literal['errextbus'], *, default:T) → bool|T

get_property(prop_name:Literal['errextbus'], **kwargs:Any) → bool

get_property(prop_name:Literal['hdl_path'], *, default:T) → str|None|T

get_property(prop_name:Literal['hdl_path'], **kwargs:Any) → str|None

get_property(prop_name:Literal['hdl_path_gate'], *, default:T) → str|None|T

get_property(prop_name:Literal['hdl_path_gate'], **kwargs:Any) → str|None

get_property(prop_name:Literal['alignment'], *, default:T) → int|None|T

get_property(prop_name:Literal['alignment'], **kwargs:Any) → int|None

get_property(prop_name:Literal['sharedextbus'], *, default:T) → bool|T

get_property(prop_name:Literal['sharedextbus'], **kwargs:Any) → bool

get_property(prop_name:Literal['name'], *, default:T) → str|T

get_property(prop_name:Literal['name'], **kwargs:Any) → str

get_property(prop_name:Literal['desc'], *, default:T) → str|None|T

get_property(prop_name:Literal['desc'], **kwargs:Any) → str|None

get_property(prop_name:Literal['ispresent'], *, default:T) → bool|T

get_property(prop_name:Literal['ispresent'], **kwargs:Any) → bool

get_property(prop_name:str, *, default:T) → Any|T

get_property(prop_name:str, **kwargs:Any) → Any

Gets the SystemRDL component property

If a property was not explicitly set in the RDL source, its default value is derived. In some cases, a default value is implied according to other property values.

Properties values that are a reference to a component instance are converted to a Node overlay object.

Parameters:

• prop_name (str) – SystemRDL property name

• default – Override built-in default value of property. If the property was not explicitly set, return this value rather than the property’s intrinsic default value.

Raises:

LookupError – If prop_name is invalid

inst:Regfile#

Reference to Component data object.

Deprecated since version 1.30: Querying the internal Component objects is no longer recommended.

Equivalents for most concepts have been made available as direct methods or properties of Node objects. It is strongly recommended to use these instead to prevent compatibility issues.

parent:AddrmapNode |RegfileNode #

Reference to parent Node

propertysize:int#

Determine the size (in bytes) of this node.

If an array, returns the size of a single element

AddrmapNode#

classsystemrdl.node.AddrmapNode(inst:AddressableComponent, env:RDLEnvironment, parent:Node |None)#

Inherits: AddressableNode

Represents an RDL addrmap

get_property(prop_name:Literal['dontcompare'], *, default:T) → bool|T#

get_property(prop_name:Literal['dontcompare'], **kwargs:Any) → bool

get_property(prop_name:Literal['donttest'], *, default:T) → bool|T

get_property(prop_name:Literal['donttest'], **kwargs:Any) → bool

get_property(prop_name:Literal['errextbus'], *, default:T) → bool|T

get_property(prop_name:Literal['errextbus'], **kwargs:Any) → bool

get_property(prop_name:Literal['hdl_path'], *, default:T) → str|None|T

get_property(prop_name:Literal['hdl_path'], **kwargs:Any) → str|None

get_property(prop_name:Literal['hdl_path_gate'], *, default:T) → str|None|T

get_property(prop_name:Literal['hdl_path_gate'], **kwargs:Any) → str|None

get_property(prop_name:Literal['alignment'], *, default:T) → int|None|T

get_property(prop_name:Literal['alignment'], **kwargs:Any) → int|None

get_property(prop_name:Literal['sharedextbus'], *, default:T) → bool|T

get_property(prop_name:Literal['sharedextbus'], **kwargs:Any) → bool

get_property(prop_name:Literal['bigendian'], *, default:T) → bool|T

get_property(prop_name:Literal['bigendian'], **kwargs:Any) → bool

get_property(prop_name:Literal['littleendian'], *, default:T) → bool|T

get_property(prop_name:Literal['littleendian'], **kwargs:Any) → bool

get_property(prop_name:Literal['addressing'], *, default:T) → AddressingType |T

get_property(prop_name:Literal['addressing'], **kwargs:Any) → AddressingType

get_property(prop_name:Literal['rsvdset'], *, default:T) → bool|T

get_property(prop_name:Literal['rsvdset'], **kwargs:Any) → bool

get_property(prop_name:Literal['rsvdsetX'], *, default:T) → bool|T

get_property(prop_name:Literal['rsvdsetX'], **kwargs:Any) → bool

get_property(prop_name:Literal['msb0'], *, default:T) → bool|T

get_property(prop_name:Literal['msb0'], **kwargs:Any) → bool

get_property(prop_name:Literal['lsb0'], *, default:T) → bool|T

get_property(prop_name:Literal['lsb0'], **kwargs:Any) → bool

get_property(prop_name:Literal['bridge'], *, default:T) → bool|T

get_property(prop_name:Literal['bridge'], **kwargs:Any) → bool

get_property(prop_name:Literal['name'], *, default:T) → str|T

get_property(prop_name:Literal['name'], **kwargs:Any) → str

get_property(prop_name:Literal['desc'], *, default:T) → str|None|T

get_property(prop_name:Literal['desc'], **kwargs:Any) → str|None

get_property(prop_name:Literal['ispresent'], *, default:T) → bool|T

get_property(prop_name:Literal['ispresent'], **kwargs:Any) → bool

get_property(prop_name:str, *, default:T) → Any|T

get_property(prop_name:str, **kwargs:Any) → Any

Gets the SystemRDL component property

If a property was not explicitly set in the RDL source, its default value is derived. In some cases, a default value is implied according to other property values.

Properties values that are a reference to a component instance are converted to a Node overlay object.

Parameters:

• prop_name (str) – SystemRDL property name

• default – Override built-in default value of property. If the property was not explicitly set, return this value rather than the property’s intrinsic default value.

Raises:

LookupError – If prop_name is invalid

inst:Addrmap#

Reference to Component data object.

Deprecated since version 1.30: Querying the internal Component objects is no longer recommended.

Equivalents for most concepts have been made available as direct methods or properties of Node objects. It is strongly recommended to use these instead to prevent compatibility issues.

parent:AddrmapNode |RootNode #

Reference to parent Node

propertysize:int#

Determine the size (in bytes) of this node.

If an array, returns the size of a single element

MemNode#

classsystemrdl.node.MemNode(inst:AddressableComponent, env:RDLEnvironment, parent:Node |None)#

Inherits: AddressableNode

Represents an RDL mem

get_property(prop_name:Literal['hdl_path_slice'], *, default:T) → List[str]|None|T#

get_property(prop_name:Literal['hdl_path_slice'], **kwargs:Any) → List[str]|None

get_property(prop_name:Literal['hdl_path_gate_slice'], *, default:T) → List[str]|None|T

get_property(prop_name:Literal['hdl_path_gate_slice'], **kwargs:Any) → List[str]|None

get_property(prop_name:Literal['sw'], *, default:T) → AccessType |T

get_property(prop_name:Literal['sw'], **kwargs:Any) → AccessType

get_property(prop_name:Literal['mementries'], *, default:T) → int|T

get_property(prop_name:Literal['mementries'], **kwargs:Any) → int

get_property(prop_name:Literal['memwidth'], *, default:T) → int|T

get_property(prop_name:Literal['memwidth'], **kwargs:Any) → int

get_property(prop_name:Literal['name'], *, default:T) → str|T

get_property(prop_name:Literal['name'], **kwargs:Any) → str

get_property(prop_name:Literal['desc'], *, default:T) → str|None|T

get_property(prop_name:Literal['desc'], **kwargs:Any) → str|None

get_property(prop_name:Literal['ispresent'], *, default:T) → bool|T

get_property(prop_name:Literal['ispresent'], **kwargs:Any) → bool

get_property(prop_name:str, *, default:T) → Any|T

get_property(prop_name:str, **kwargs:Any) → Any

Gets the SystemRDL component property

If a property was not explicitly set in the RDL source, its default value is derived. In some cases, a default value is implied according to other property values.

Properties values that are a reference to a component instance are converted to a Node overlay object.

Parameters:

• prop_name (str) – SystemRDL property name

• default – Override built-in default value of property. If the property was not explicitly set, return this value rather than the property’s intrinsic default value.

Raises:

LookupError – If prop_name is invalid

inst:Mem#

Reference to Component data object.

Deprecated since version 1.30: Querying the internal Component objects is no longer recommended.

Equivalents for most concepts have been made available as direct methods or properties of Node objects. It is strongly recommended to use these instead to prevent compatibility issues.

propertyis_sw_readable:bool#

Memory is readable by software

Added in version 1.21.

propertyis_sw_writable:bool#

Memory is writable by software

Added in version 1.21.

parent:AddrmapNode #

Reference to parent Node

propertysize:int#

Determine the size (in bytes) of this node.

If an array, returns the size of a single element

RootNode#

classsystemrdl.node.RootNode(inst:Component, env:RDLEnvironment, parent:Node |None)#

Inherits: Node

Pseudo-node that represents the root namespace of a compiled design.

This is does not represent any actual design hierarchy. It is merely a convenient container for the following children:

• Zero or more SignalNode that are instantiated in the root namespace

• Exactly one top-level AddrmapNode.

inst:Root#

Reference to Component data object.

Deprecated since version 1.30: Querying the internal Component objects is no longer recommended.

Equivalents for most concepts have been made available as direct methods or properties of Node objects. It is strongly recommended to use these instead to prevent compatibility issues.

parent:None#

RootNode never has a parent, so this attribute is always None

propertytop:AddrmapNode #

Returns the top-level addrmap node

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