LLVM: lib/Target/X86/X86TargetMachine.cpp Source File

LLVM 22.0.0git
X86TargetMachine.cpp
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1//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the X86 specific subclass of TargetMachine.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86TargetMachine.h"
14#include "MCTargetDesc/X86MCTargetDesc.h"
15#include "TargetInfo/X86TargetInfo.h"
16#include "X86.h"
17#include "X86MachineFunctionInfo.h"
18#include "X86MacroFusion.h"
19#include "X86Subtarget.h"
20#include "X86TargetObjectFile.h"
21#include "X86TargetTransformInfo.h"
22#include "llvm-c/Visibility.h"
23#include "llvm/ADT/SmallString.h"
24#include "llvm/ADT/StringRef.h"
25#include "llvm/Analysis/TargetTransformInfo.h"
26#include "llvm/CodeGen/ExecutionDomainFix.h"
27#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
28#include "llvm/CodeGen/GlobalISel/CallLowering.h"
29#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31#include "llvm/CodeGen/GlobalISel/Legalizer.h"
32#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33#include "llvm/CodeGen/MIRParser/MIParser.h"
34#include "llvm/CodeGen/MIRYamlMapping.h"
35#include "llvm/CodeGen/MachineScheduler.h"
36#include "llvm/CodeGen/Passes.h"
37#include "llvm/CodeGen/TargetPassConfig.h"
38#include "llvm/IR/Attributes.h"
39#include "llvm/IR/DataLayout.h"
40#include "llvm/IR/Function.h"
41#include "llvm/MC/MCAsmInfo.h"
42#include "llvm/MC/TargetRegistry.h"
43#include "llvm/Pass.h"
44#include "llvm/Support/CodeGen.h"
45#include "llvm/Support/CommandLine.h"
46#include "llvm/Support/ErrorHandling.h"
47#include "llvm/Target/TargetLoweringObjectFile.h"
48#include "llvm/Target/TargetOptions.h"
49#include "llvm/TargetParser/Triple.h"
50#include "llvm/Transforms/CFGuard.h"
51#include <memory>
52#include <optional>
53#include <string>
54
55using namespace llvm;
56
57 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
58 cl::desc("Enable the machine combiner pass"),
59 cl::init(true), cl::Hidden);
60
61static cl::opt<bool>
62 EnableTileRAPass("x86-tile-ra",
63 cl::desc("Enable the tile register allocation pass"),
64 cl::init(true), cl::Hidden);
65
67 // Register the target.
70
111}
112
113 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
114 if (TT.isOSBinFormatMachO()) {
115 if (TT.isX86_64())
116 return std::make_unique<X86_64MachoTargetObjectFile>();
117 return std::make_unique<TargetLoweringObjectFileMachO>();
118 }
119
120 if (TT.isOSBinFormatCOFF())
121 return std::make_unique<TargetLoweringObjectFileCOFF>();
122
123 if (TT.isX86_64())
124 return std::make_unique<X86_64ELFTargetObjectFile>();
125 return std::make_unique<X86ELFTargetObjectFile>();
126}
127
128 static Reloc::Model getEffectiveRelocModel(const Triple &TT, bool JIT,
129 std::optional<Reloc::Model> RM) {
130 bool is64Bit = TT.isX86_64();
131 if (!RM) {
132 // JIT codegen should use static relocations by default, since it's
133 // typically executed in process and not relocatable.
134 if (JIT)
135 return Reloc::Static;
136
137 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
138 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
139 // use static relocation model by default.
140 if (TT.isOSDarwin()) {
141 if (is64Bit)
142 return Reloc::PIC_;
143 return Reloc::DynamicNoPIC;
144 }
145 if (TT.isOSWindows() && is64Bit)
146 return Reloc::PIC_;
147 return Reloc::Static;
148 }
149
150 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
151 // is defined as a model for code which may be used in static or dynamic
152 // executables but not necessarily a shared library. On X86-32 we just
153 // compile in -static mode, in x86-64 we use PIC.
154 if (*RM == Reloc::DynamicNoPIC) {
155 if (is64Bit)
156 return Reloc::PIC_;
157 if (!TT.isOSDarwin())
158 return Reloc::Static;
159 }
160
161 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
162 // the Mach-O file format doesn't support it.
163 if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
164 return Reloc::PIC_;
165
166 return *RM;
167}
168
169static CodeModel::Model
170 getEffectiveX86CodeModel(const Triple &TT, std::optional<CodeModel::Model> CM,
171 bool JIT) {
172 bool Is64Bit = TT.isX86_64();
173 if (CM) {
174 if (*CM == CodeModel::Tiny)
175 reportFatalUsageError("target does not support the tiny CodeModel");
176 return *CM;
177 }
178 if (JIT)
179 return Is64Bit ? CodeModel::Large : CodeModel::Small;
180 return CodeModel::Small;
181}
182
183/// Create an X86 target.
184///
186 StringRef CPU, StringRef FS,
187 const TargetOptions &Options,
188 std::optional<Reloc::Model> RM,
189 std::optional<CodeModel::Model> CM,
190 CodeGenOptLevel OL, bool JIT)
191 : CodeGenTargetMachineImpl(T, TT.computeDataLayout(), TT, CPU, FS, Options,
192 getEffectiveRelocModel(TT, JIT, RM),
193 getEffectiveX86CodeModel(TT, CM, JIT), OL),
194 TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
195 // On PS4/PS5, the "return address" of a 'noreturn' call must still be within
196 // the calling function. Note that this also includes __stack_chk_fail,
197 // so there was some target-specific logic in the instruction selectors
198 // to handle that. That code has since been generalized, so the only thing
199 // needed is to set TrapUnreachable here.
200 if (TT.isPS() || TT.isOSBinFormatMachO()) {
201 this->Options.TrapUnreachable = true;
202 this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
203 }
204
205 setMachineOutliner(true);
206
207 // x86 supports the debug entry values.
209
210 initAsmInfo();
211}
212
213X86TargetMachine::~X86TargetMachine() = default;
214
215const X86Subtarget *
217 Attribute CPUAttr = F.getFnAttribute("target-cpu");
218 Attribute TuneAttr = F.getFnAttribute("tune-cpu");
219 Attribute FSAttr = F.getFnAttribute("target-features");
220
221 StringRef CPU =
222 CPUAttr.isValid() ? CPUAttr.getValueAsString() : (StringRef)TargetCPU;
223 // "x86-64" is a default target setting for many front ends. In these cases,
224 // they actually request for "generic" tuning unless the "tune-cpu" was
225 // specified.
226 StringRef TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString()
227 : CPU == "x86-64" ? "generic"
228 : (StringRef)CPU;
229 StringRef FS =
230 FSAttr.isValid() ? FSAttr.getValueAsString() : (StringRef)TargetFS;
231
233 // The additions here are ordered so that the definitely short strings are
234 // added first so we won't exceed the small size. We append the
235 // much longer FS string at the end so that we only heap allocate at most
236 // one time.
237
238 // Extract prefer-vector-width attribute.
239 unsigned PreferVectorWidthOverride = 0;
240 Attribute PreferVecWidthAttr = F.getFnAttribute("prefer-vector-width");
241 if (PreferVecWidthAttr.isValid()) {
242 StringRef Val = PreferVecWidthAttr.getValueAsString();
243 unsigned Width;
244 if (!Val.getAsInteger(0, Width)) {
245 Key += 'p';
246 Key += Val;
247 PreferVectorWidthOverride = Width;
248 }
249 }
250
251 // Extract min-legal-vector-width attribute.
252 unsigned RequiredVectorWidth = UINT32_MAX;
253 Attribute MinLegalVecWidthAttr = F.getFnAttribute("min-legal-vector-width");
254 if (MinLegalVecWidthAttr.isValid()) {
255 StringRef Val = MinLegalVecWidthAttr.getValueAsString();
256 unsigned Width;
257 if (!Val.getAsInteger(0, Width)) {
258 Key += 'm';
259 Key += Val;
260 RequiredVectorWidth = Width;
261 }
262 }
263
264 // Add CPU to the Key.
265 Key += CPU;
266
267 // Add tune CPU to the Key.
268 Key += TuneCPU;
269
270 // Keep track of the start of the feature portion of the string.
271 unsigned FSStart = Key.size();
272
273 // FIXME: This is related to the code below to reset the target options,
274 // we need to know whether or not the soft float flag is set on the
275 // function before we can generate a subtarget. We also need to use
276 // it as a key for the subtarget since that can be the only difference
277 // between two functions.
278 bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
279 // If the soft float attribute is set on the function turn on the soft float
280 // subtarget feature.
281 if (SoftFloat)
282 Key += FS.empty() ? "+soft-float" : "+soft-float,";
283
284 Key += FS;
285
286 // We may have added +soft-float to the features so move the StringRef to
287 // point to the full string in the Key.
288 FS = Key.substr(FSStart);
289
290 auto &I = SubtargetMap[Key];
291 if (!I) {
292 // This needs to be done before we create a new subtarget since any
293 // creation will depend on the TM and the code generation flags on the
294 // function that reside in TargetOptions.
296 I = std::make_unique<X86Subtarget>(
297 TargetTriple, CPU, TuneCPU, FS, *this,
298 MaybeAlign(F.getParent()->getOverrideStackAlignment()),
299 PreferVectorWidthOverride, RequiredVectorWidth);
300 }
301 return I.get();
302}
303
307
308yaml::MachineFunctionInfo *
310 const auto *MFI = MF.getInfo<X86MachineFunctionInfo>();
311 return new yaml::X86MachineFunctionInfo(*MFI);
312}
313
316 SMDiagnostic &Error, SMRange &SourceRange) const {
317 const auto &YamlMFI = static_cast<const yaml::X86MachineFunctionInfo &>(MFI);
318 PFS.MF.getInfo<X86MachineFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
319 return false;
320}
321
323 unsigned DestAS) const {
324 assert(SrcAS != DestAS && "Expected different address spaces!");
325 if (getPointerSize(SrcAS) != getPointerSize(DestAS))
326 return false;
327 return SrcAS < 256 && DestAS < 256;
328}
329
330void X86TargetMachine::reset() { SubtargetMap.clear(); }
331
332ScheduleDAGInstrs *
338
339ScheduleDAGInstrs *
345
346//===----------------------------------------------------------------------===//
347// X86 TTI query.
348//===----------------------------------------------------------------------===//
349
350TargetTransformInfo
352 return TargetTransformInfo(std::make_unique<X86TTIImpl>(this, F));
353}
354
355//===----------------------------------------------------------------------===//
356// Pass Pipeline Configuration
357//===----------------------------------------------------------------------===//
358
359namespace {
360
361/// X86 Code Generator Pass Configuration Options.
362class X86PassConfig : public TargetPassConfig {
363public:
364 X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
365 : TargetPassConfig(TM, PM) {}
366
367 X86TargetMachine &getX86TargetMachine() const {
368 return getTM<X86TargetMachine>();
369 }
370
371 void addIRPasses() override;
372 bool addInstSelector() override;
373 bool addIRTranslator() override;
374 bool addLegalizeMachineIR() override;
375 bool addRegBankSelect() override;
376 bool addGlobalInstructionSelect() override;
377 bool addILPOpts() override;
378 bool addPreISel() override;
379 void addMachineSSAOptimization() override;
380 void addPreRegAlloc() override;
381 bool addPostFastRegAllocRewrite() override;
382 void addPostRegAlloc() override;
383 void addPreEmitPass() override;
384 void addPreEmitPass2() override;
385 void addPreSched2() override;
386 bool addRegAssignAndRewriteOptimized() override;
387
388 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
389};
390
391class X86ExecutionDomainFix : public ExecutionDomainFix {
392public:
393 static char ID;
394 X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
395 StringRef getPassName() const override {
396 return "X86 Execution Dependency Fix";
397 }
398};
399char X86ExecutionDomainFix::ID;
400
401} // end anonymous namespace
402
403 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
404 "X86 Execution Domain Fix", false, false)
405INITIALIZE_PASS_DEPENDENCY(ReachingDefInfoWrapperPass)
406 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
407 "X86 Execution Domain Fix", false, false)
408
410 return new X86PassConfig(*this, PM);
411}
412
419
420void X86PassConfig::addIRPasses() {
421 addPass(createAtomicExpandLegacyPass());
422
423 // We add both pass anyway and when these two passes run, we skip the pass
424 // based on the option level and option attribute.
425 addPass(createX86LowerAMXIntrinsicsLegacyPass());
426 addPass(createX86LowerAMXTypeLegacyPass());
427
428 TargetPassConfig::addIRPasses();
429
430 if (TM->getOptLevel() != CodeGenOptLevel::None) {
431 addPass(createInterleavedAccessPass());
432 addPass(createX86PartialReductionLegacyPass());
433 }
434
435 // Add passes that handle indirect branch removal and insertion of a retpoline
436 // thunk. These will be a no-op unless a function subtarget has the retpoline
437 // feature enabled.
438 addPass(createIndirectBrExpandPass());
439
440 // Add Control Flow Guard checks.
441 const Triple &TT = TM->getTargetTriple();
442 if (TT.isOSWindows()) {
443 if (TT.isX86_64()) {
444 addPass(createCFGuardDispatchPass());
445 } else {
446 addPass(createCFGuardCheckPass());
447 }
448 }
449
450 if (TM->Options.JMCInstrument)
451 addPass(createJMCInstrumenterPass());
452}
453
454bool X86PassConfig::addInstSelector() {
455 // Install an instruction selector.
456 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
457
458 // For ELF, cleanup any local-dynamic TLS accesses.
459 if (TM->getTargetTriple().isOSBinFormatELF() &&
460 getOptLevel() != CodeGenOptLevel::None)
461 addPass(createCleanupLocalDynamicTLSPass());
462
463 addPass(createX86GlobalBaseRegPass());
464 addPass(createX86ArgumentStackSlotPass());
465 return false;
466}
467
468bool X86PassConfig::addIRTranslator() {
469 addPass(new IRTranslator(getOptLevel()));
470 return false;
471}
472
473bool X86PassConfig::addLegalizeMachineIR() {
474 addPass(new Legalizer());
475 return false;
476}
477
478bool X86PassConfig::addRegBankSelect() {
479 addPass(new RegBankSelect());
480 return false;
481}
482
483bool X86PassConfig::addGlobalInstructionSelect() {
484 addPass(new InstructionSelect(getOptLevel()));
485 // Add GlobalBaseReg in case there is no SelectionDAG passes afterwards
486 if (isGlobalISelAbortEnabled())
487 addPass(createX86GlobalBaseRegPass());
488 return false;
489}
490
491bool X86PassConfig::addILPOpts() {
492 addPass(&EarlyIfConverterLegacyID);
493 if (EnableMachineCombinerPass)
494 addPass(&MachineCombinerID);
495 addPass(createX86CmovConverterPass());
496 return true;
497}
498
499bool X86PassConfig::addPreISel() {
500 // Only add this pass for 32-bit x86 Windows.
501 const Triple &TT = TM->getTargetTriple();
502 if (TT.isOSWindows() && TT.isX86_32())
503 addPass(createX86WinEHStatePass());
504 return true;
505}
506
507void X86PassConfig::addPreRegAlloc() {
508 if (getOptLevel() != CodeGenOptLevel::None) {
509 addPass(&LiveRangeShrinkID);
510 addPass(createX86FixupSetCC());
511 addPass(createX86OptimizeLEAs());
512 addPass(createX86CallFrameOptimization());
513 addPass(createX86AvoidStoreForwardingBlocks());
514 }
515
516 addPass(createX86SuppressAPXForRelocationPass());
517
518 addPass(createX86SpeculativeLoadHardeningPass());
519 addPass(createX86FlagsCopyLoweringPass());
520 addPass(createX86DynAllocaExpander());
521
522 if (getOptLevel() != CodeGenOptLevel::None)
523 addPass(createX86PreTileConfigPass());
524 else
525 addPass(createX86FastPreTileConfigPass());
526}
527
528void X86PassConfig::addMachineSSAOptimization() {
529 addPass(createX86DomainReassignmentPass());
530 TargetPassConfig::addMachineSSAOptimization();
531}
532
533void X86PassConfig::addPostRegAlloc() {
534 addPass(createX86LowerTileCopyPass());
535 addPass(createX86FloatingPointStackifierPass());
536 // When -O0 is enabled, the Load Value Injection Hardening pass will fall back
537 // to using the Speculative Execution Side Effect Suppression pass for
538 // mitigation. This is to prevent slow downs due to
539 // analyses needed by the LVIHardening pass when compiling at -O0.
540 if (getOptLevel() != CodeGenOptLevel::None)
541 addPass(createX86LoadValueInjectionLoadHardeningPass());
542}
543
544void X86PassConfig::addPreSched2() {
545 addPass(createX86ExpandPseudoPass());
546 addPass(createKCFIPass());
547}
548
549void X86PassConfig::addPreEmitPass() {
550 if (getOptLevel() != CodeGenOptLevel::None) {
551 addPass(new X86ExecutionDomainFix());
552 addPass(createBreakFalseDeps());
553 }
554
555 addPass(createX86IndirectBranchTrackingPass());
556
557 addPass(createX86IssueVZeroUpperPass());
558
559 if (getOptLevel() != CodeGenOptLevel::None) {
560 addPass(createX86FixupBWInsts());
561 addPass(createX86PadShortFunctions());
562 addPass(createX86FixupLEAs());
563 addPass(createX86FixupInstTuning());
564 addPass(createX86FixupVectorConstants());
565 }
566 addPass(createX86CompressEVEXPass());
567 addPass(createX86DiscriminateMemOpsPass());
568 addPass(createX86InsertPrefetchPass());
569 addPass(createX86InsertX87waitPass());
570}
571
572void X86PassConfig::addPreEmitPass2() {
573 const Triple &TT = TM->getTargetTriple();
574 const MCAsmInfo *MAI = TM->getMCAsmInfo();
575
576 // The X86 Speculative Execution Pass must run after all control
577 // flow graph modifying passes. As a result it was listed to run right before
578 // the X86 Retpoline Thunks pass. The reason it must run after control flow
579 // graph modifications is that the model of LFENCE in LLVM has to be updated
580 // (FIXME: https://bugs.llvm.org/show_bug.cgi?id=45167). Currently the
581 // placement of this pass was hand checked to ensure that the subsequent
582 // passes don't move the code around the LFENCEs in a way that will hurt the
583 // correctness of this pass. This placement has been shown to work based on
584 // hand inspection of the codegen output.
585 addPass(createX86SpeculativeExecutionSideEffectSuppression());
586 addPass(createX86IndirectThunksPass());
587 addPass(createX86ReturnThunksPass());
588
589 // Insert extra int3 instructions after trailing call instructions to avoid
590 // issues in the unwinder.
591 if (TT.isOSWindows() && TT.isX86_64())
592 addPass(createX86AvoidTrailingCallPass());
593
594 // Verify basic block incoming and outgoing cfa offset and register values and
595 // correct CFA calculation rule where needed by inserting appropriate CFI
596 // instructions.
597 if (!TT.isOSDarwin() &&
598 (!TT.isOSWindows() ||
599 MAI->getExceptionHandlingType() == ExceptionHandling::DwarfCFI))
600 addPass(createCFIInstrInserter());
601
602 if (TT.isOSWindows()) {
603 // Identify valid longjmp targets for Windows Control Flow Guard.
604 addPass(createCFGuardLongjmpPass());
605 // Identify valid eh continuation targets for Windows EHCont Guard.
606 addPass(createEHContGuardTargetsPass());
607 }
608 addPass(createX86LoadValueInjectionRetHardeningPass());
609
610 // Insert pseudo probe annotation for callsite profiling
611 addPass(createPseudoProbeInserter());
612
613 // KCFI indirect call checks are lowered to a bundle, and on Darwin platforms,
614 // also CALL_RVMARKER.
615 addPass(createUnpackMachineBundles([&TT](const MachineFunction &MF) {
616 // Only run bundle expansion if the module uses kcfi, or there are relevant
617 // ObjC runtime functions present in the module.
618 const Function &F = MF.getFunction();
619 const Module *M = F.getParent();
620 return M->getModuleFlag("kcfi") ||
621 (TT.isOSDarwin() &&
622 (M->getFunction("objc_retainAutoreleasedReturnValue") ||
623 M->getFunction("objc_unsafeClaimAutoreleasedReturnValue")));
624 }));
625
626 // Analyzes and emits pseudos to support Win x64 Unwind V2. This pass must run
627 // after all real instructions have been added to the epilog.
628 if (TT.isOSWindows() && TT.isX86_64())
629 addPass(createX86WinEHUnwindV2Pass());
630}
631
632bool X86PassConfig::addPostFastRegAllocRewrite() {
633 addPass(createX86FastTileConfigPass());
634 return true;
635}
636
637std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
638 return getStandardCSEConfigForOpt(TM->getOptLevel());
639}
640
643 const Register Reg) {
644 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
645 return static_cast<const X86RegisterInfo &>(TRI).isTileRegisterClass(RC);
646}
647
648bool X86PassConfig::addRegAssignAndRewriteOptimized() {
649 // Don't support tile RA when RA is specified by command line "-regalloc".
650 if (!isCustomizedRegAlloc() && EnableTileRAPass) {
651 // Allocate tile register first.
652 addPass(createGreedyRegisterAllocator(onlyAllocateTileRegisters));
653 addPass(createX86TileConfigPass());
654 }
655 return TargetPassConfig::addRegAssignAndRewriteOptimized();
656}
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
static Reloc::Model getEffectiveRelocModel()
This file contains the simple types necessary to represent the attributes associated with functions a...
Provides analysis for continuously CSEing during GISel passes.
This file describes how to lower LLVM calls to machine code calls.
DXIL Legalizer
This file declares the IRTranslator pass.
F
#define F(x, y, z)
Definition MD5.cpp:55
I
#define I(x, y, z)
Definition MD5.cpp:58
Register Reg
Register const TargetRegisterInfo * TRI
T
#define T
static cl::opt< bool > EnableMachineCombinerPass("ppc-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition PassSupport.h:42
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition PassSupport.h:44
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition PassSupport.h:39
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
const GCNTargetMachine & getTM(const GCNSubtarget *STI)
This file defines the SmallString class.
Y
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
X
static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
static std::unique_ptr< TargetLoweringObjectFile > createTLOF()
#define LLVM_C_ABI
LLVM_C_ABI is the export/visibility macro used to mark symbols declared in llvm-c as exported when bu...
Definition Visibility.h:40
static bool is64Bit(const char *name)
static cl::opt< bool > EnableTileRAPass("x86-tile-ra", cl::desc("Enable the tile register allocation pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableMachineCombinerPass("x86-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static CodeModel::Model getEffectiveX86CodeModel(const Triple &TT, std::optional< CodeModel::Model > CM, bool JIT)
static bool onlyAllocateTileRegisters(const TargetRegisterInfo &TRI, const MachineRegisterInfo &MRI, const Register Reg)
LLVM_C_ABI void LLVMInitializeX86Target()
This file a TargetTransformInfoImplBase conforming object specific to the X86 target machine.
Functions, function parameters, and return types can have attributes to indicate how they should be t...
Definition Attributes.h:69
LLVM_ABI StringRef getValueAsString() const
Return the attribute's value as a string.
Definition Attributes.cpp:400
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition Attributes.h:223
CodeGenTargetMachineImpl(const Target &T, StringRef DataLayoutString, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOptLevel OL)
virtual void reset()
Reset internal state.
Lightweight error class with error context and mandatory checking.
Definition Error.h:159
This pass is responsible for selecting generic machine instructions to target-specific instructions.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition MCAsmInfo.h:64
ExceptionHandling getExceptionHandlingType() const
Definition MCAsmInfo.h:633
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition Module.h:67
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition PassRegistry.h:38
static LLVM_ABI PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition RegBankSelect.h:91
Wrapper class representing virtual and physical registers.
Definition Register.h:20
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition SourceMgr.h:297
Represents a range in source code.
Definition SMLoc.h:47
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition SmallString.h:26
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition StringRef.h:472
void setSupportsDebugEntryValues(bool Enable)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
const Triple & getTargetTriple() const
void setMachineOutliner(bool Enable)
Reloc::Model RM
unsigned getPointerSize(unsigned AS) const
Get the pointer size for this target.
std::string TargetFS
std::string TargetCPU
std::unique_ptr< const MCSubtargetInfo > STI
TargetOptions Options
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Target-Independent Code Generator Pass Configuration Options.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
virtual bool addRegAssignAndRewriteOptimized()
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition Triple.h:47
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
const X86Subtarget * getSubtargetImpl() const =delete
ScheduleDAGInstrs * createMachineScheduler(MachineSchedContext *C) const override
Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this ...
ScheduleDAGInstrs * createPostMachineScheduler(MachineSchedContext *C) const override
Similar to createMachineScheduler but used when postRA machine scheduling is enabled.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
~X86TargetMachine() override
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
Create an X86 target.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition CallingConv.h:24
@ C
The default llvm calling convention, compatible with C.
Definition CallingConv.h:34
@ Static
Definition CodeGen.h:25
@ DynamicNoPIC
Definition CodeGen.h:25
@ X86
Windows x64, Windows Itanium (IA-64)
Definition MCAsmInfo.h:50
initializer< Ty > init(const Ty &Val)
Definition CommandLine.h:445
This is an optimization pass for GlobalISel generic memory operations.
Definition AddressRanges.h:18
FunctionPass * createX86FloatingPointStackifierPass()
This function returns a pass which converts floating-point register references and pseudo instruction...
ScheduleDAGMILive * createSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
LLVM_ABI FunctionPass * createIndirectBrExpandPass()
FunctionPass * createX86WinEHStatePass()
Return an IR pass that inserts EH registration stack objects and explicit EH state updates.
void initializeX86TileConfigPass(PassRegistry &)
FunctionPass * createX86LowerAMXIntrinsicsLegacyPass()
void initializeX86PartialReductionLegacyPass(PassRegistry &)
FunctionPass * createX86SuppressAPXForRelocationPass()
void initializeX86CallFrameOptimizationPass(PassRegistry &)
LLVM_ABI ModulePass * createJMCInstrumenterPass()
JMC instrument pass.
void initializeFixupBWInstPassPass(PassRegistry &)
void initializeX86LoadValueInjectionRetHardeningPassPass(PassRegistry &)
FunctionPass * createX86LoadValueInjectionLoadHardeningPass()
FunctionPass * createX86IssueVZeroUpperPass()
This pass inserts AVX vzeroupper instructions before each call to avoid transition penalty between fu...
LLVM_ABI FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
void initializeX86ArgumentStackSlotPassPass(PassRegistry &)
void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &)
void initializeWinEHStatePassPass(PassRegistry &)
FunctionPass * createX86InsertPrefetchPass()
This pass applies profiling information to insert cache prefetches.
@ DwarfCFI
DWARF-like instruction based exceptions.
Definition CodeGen.h:55
LLVM_ABI FunctionPass * createPseudoProbeInserter()
This pass inserts pseudo probe annotation for callsite profiling.
Target & getTheX86_32Target()
FunctionPass * createX86GlobalBaseRegPass()
This pass initializes a global base register for PIC on x86-32.
FunctionPass * createX86FixupBWInsts()
Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...
void initializeX86LowerAMXIntrinsicsLegacyPassPass(PassRegistry &)
FunctionPass * createX86DomainReassignmentPass()
Return a Machine IR pass that reassigns instruction chains from one domain to another,...
FunctionPass * createX86LoadValueInjectionRetHardeningPass()
FunctionPass * createX86SpeculativeExecutionSideEffectSuppression()
FunctionPass * createX86PartialReductionLegacyPass()
FunctionPass * createCleanupLocalDynamicTLSPass()
This pass combines multiple accesses to local-dynamic TLS variables so that the TLS base address for ...
FunctionPass * createX86FlagsCopyLoweringPass()
Return a pass that lowers EFLAGS copy pseudo instructions.
void initializeX86FastTileConfigPass(PassRegistry &)
FunctionPass * createCFGuardDispatchPass()
Insert Control FLow Guard dispatches on indirect function calls.
Definition CFGuard.cpp:312
LLVM_ABI std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOptLevel Level)
Definition CSEInfo.cpp:89
FunctionPass * createX86CompressEVEXPass()
This pass compress instructions from EVEX space to legacy/VEX/EVEX space when possible in order to re...
void initializeX86ExpandPseudoPass(PassRegistry &)
void initializeX86AvoidTrailingCallPassPass(PassRegistry &)
FunctionPass * createX86ArgumentStackSlotPass()
void initializeX86PreTileConfigPass(PassRegistry &)
LLVM_ABI char & EarlyIfConverterLegacyID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
FunctionPass * createX86CmovConverterPass()
This pass converts X86 cmov instructions into branch when profitable.
FunctionPass * createX86TileConfigPass()
Return a pass that config the tile registers.
FunctionPass * createX86PadShortFunctions()
Return a pass that pads short functions with NOOPs.
void initializeX86DomainReassignmentPass(PassRegistry &)
void initializeX86LoadValueInjectionLoadHardeningPassPass(PassRegistry &)
void initializeX86SuppressAPXForRelocationPassPass(PassRegistry &)
FunctionPass * createX86FastPreTileConfigPass()
Return a pass that preconfig the tile registers before fast reg allocation.
std::unique_ptr< ScheduleDAGMutation > createX86MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createX86MacroFusionDAGMutation()); to X86TargetMachine::c...
void initializeX86AvoidSFBPassPass(PassRegistry &)
FunctionPass * createX86LowerTileCopyPass()
Return a pass that lower the tile copy instruction.
LLVM_ABI char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
void initializeX86FastPreTileConfigPass(PassRegistry &)
static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
FunctionPass * createX86SpeculativeLoadHardeningPass()
FunctionPass * createX86FixupSetCC()
Return a pass that transforms setcc + movzx pairs into xor + setcc.
FunctionPass * createX86IndirectBranchTrackingPass()
This pass inserts ENDBR instructions before indirect jump/call destinations as part of CET IBT mechan...
void initializeX86AsmPrinterPass(PassRegistry &)
FunctionPass * createX86InsertX87waitPass()
This pass insert wait instruction after X87 instructions which could raise fp exceptions when strict-...
ScheduleDAGMI * createSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
void initializeX86FixupSetCCPassPass(PassRegistry &)
LLVM_ABI FunctionPass * createKCFIPass()
Lowers KCFI operand bundles for indirect calls.
Definition KCFI.cpp:61
LLVM_ABI char & LiveRangeShrinkID
LiveRangeShrink pass.
FunctionPass * createX86ExpandPseudoPass()
Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...
FunctionPass * createX86FixupInstTuning()
Return a pass that replaces equivalent slower instructions with faster ones.
void initializeX86WinEHUnwindV2Pass(PassRegistry &)
FunctionPass * createX86ISelDag(X86TargetMachine &TM, CodeGenOptLevel OptLevel)
This pass converts a legalized DAG into a X86-specific DAG, ready for instruction scheduling.
void initializeX86LowerTileCopyPass(PassRegistry &)
void initializeX86OptimizeLEAPassPass(PassRegistry &)
LLVM_ABI void initializePseudoProbeInserterPass(PassRegistry &)
CodeGenOptLevel
Code generation optimization level.
Definition CodeGen.h:82
LLVM_ABI FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
LLVM_ATTRIBUTE_VISIBILITY_DEFAULT AnalysisKey InnerAnalysisManagerProxy< AnalysisManagerT, IRUnitT, ExtraArgTs... >::Key
Definition PassManager.h:668
FunctionPass * createX86FastTileConfigPass()
Return a pass that config the tile registers after fast reg allocation.
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec,...
LLVM_ABI FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
LLVM_ABI void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition GlobalISel.cpp:17
LLVM_ABI void initializeKCFIPass(PassRegistry &)
void initializeX86FixupInstTuningPassPass(PassRegistry &)
void initializeX86LowerAMXTypeLegacyPassPass(PassRegistry &)
void initializeX86CmovConverterPassPass(PassRegistry &)
LLVM_ABI FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
FunctionPass * createX86CallFrameOptimization()
Return a pass that optimizes the code-size of x86 call sequences.
void initializeX86FlagsCopyLoweringPassPass(PassRegistry &)
void initializeFPSPass(PassRegistry &)
LLVM_ABI FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
FunctionPass * createX86WinEHUnwindV2Pass()
// Analyzes and emits pseudos to support Win x64 Unwind V2.
FunctionPass * createX86LowerAMXTypeLegacyPass()
FunctionPass * createX86AvoidTrailingCallPass()
Return a pass that inserts int3 at the end of the function if it ends with a CALL instruction.
FunctionPass * createX86DynAllocaExpander()
Return a pass that expands DynAlloca pseudo-instructions.
void initializeX86SpeculativeExecutionSideEffectSuppressionPass(PassRegistry &)
void initializeCompressEVEXPassPass(PassRegistry &)
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
Definition CFGuard.cpp:308
LLVM_ABI FunctionPass * createEHContGuardTargetsPass()
Creates Windows EH Continuation Guard target identification pass.
FunctionPass * createX86OptimizeLEAs()
Return a pass that removes redundant LEA instructions and redundant address recalculations.
void initializeX86FixupVectorConstantsPassPass(PassRegistry &)
FunctionPass * createX86IndirectThunksPass()
This pass creates the thunks for the retpoline feature.
LLVM_ABI FunctionPass * createAtomicExpandLegacyPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
BumpPtrAllocatorImpl<> BumpPtrAllocator
The standard BumpPtrAllocator which just uses the default template parameters.
Definition Allocator.h:383
void initializeX86DynAllocaExpanderPass(PassRegistry &)
Target & getTheX86_64Target()
FunctionPass * createX86FixupVectorConstants()
Return a pass that reduces the size of vector constant pool loads.
LLVM_ABI FunctionPass * createCFIInstrInserter()
Creates CFI Instruction Inserter pass.
void initializeX86ExecutionDomainFixPass(PassRegistry &)
FunctionPass * createX86PreTileConfigPass()
Return a pass that insert pseudo tile config instruction.
FunctionPass * createX86ReturnThunksPass()
This pass replaces ret instructions with jmp's to __x86_return thunk.
FunctionPass * createX86AvoidStoreForwardingBlocks()
Return a pass that avoids creating store forward block issues in the hardware.
void initializeX86ReturnThunksPass(PassRegistry &)
void initializeX86DAGToDAGISelLegacyPass(PassRegistry &)
FunctionPass * createX86DiscriminateMemOpsPass()
This pass ensures instructions featuring a memory operand have distinctive <LineNumber,...
void initializeFixupLEAPassPass(PassRegistry &)
LLVM_ABI void reportFatalUsageError(Error Err)
Report a fatal error that does not indicate a bug in LLVM.
Definition Error.cpp:180
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
static FuncInfoTy * create(BumpPtrAllocator &Allocator, const Function &F, const SubtargetTy *STI)
Factory function: default behavior is to call new using the supplied allocator.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition Alignment.h:106
MachineFunction & MF
Definition MIParser.h:167
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
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