1//===-- X86DisassemblerDecoderInternal.h - Disassembler decoder -*- C++ -*-===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7//===----------------------------------------------------------------------===//
9// This file is part of the X86 Disassembler.
10// It contains the public interface of the instruction decoder.
11// Documentation for the disassembler can be found in X86Disassembler.h.
13//===----------------------------------------------------------------------===//
15#ifndef LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H
16#define LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H
24 #define bitFromOffset0(val) ((val) & 0x1)
25 #define bitFromOffset1(val) (((val) >> 1) & 0x1)
26 #define bitFromOffset2(val) (((val) >> 2) & 0x1)
27 #define bitFromOffset3(val) (((val) >> 3) & 0x1)
28 #define bitFromOffset4(val) (((val) >> 4) & 0x1)
29 #define bitFromOffset5(val) (((val) >> 5) & 0x1)
30 #define bitFromOffset6(val) (((val) >> 6) & 0x1)
31 #define bitFromOffset7(val) (((val) >> 7) & 0x1)
32 #define twoBitsFromOffset0(val) ((val) & 0x3)
33 #define twoBitsFromOffset6(val) (((val) >> 6) & 0x3)
34 #define threeBitsFromOffset0(val) ((val) & 0x7)
35 #define threeBitsFromOffset3(val) (((val) >> 3) & 0x7)
36 #define fourBitsFromOffset0(val) ((val) & 0xf)
37 #define fourBitsFromOffset3(val) (((val) >> 3) & 0xf)
38 #define fiveBitsFromOffset0(val) ((val) & 0x1f)
39 #define invertedBitFromOffset2(val) (((~(val)) >> 2) & 0x1)
40 #define invertedBitFromOffset3(val) (((~(val)) >> 3) & 0x1)
41 #define invertedBitFromOffset4(val) (((~(val)) >> 4) & 0x1)
42 #define invertedBitFromOffset5(val) (((~(val)) >> 5) & 0x1)
43 #define invertedBitFromOffset6(val) (((~(val)) >> 6) & 0x1)
44 #define invertedBitFromOffset7(val) (((~(val)) >> 7) & 0x1)
45 #define invertedFourBitsFromOffset3(val) (((~(val)) >> 3) & 0xf)
47 #define modFromModRM(modRM) twoBitsFromOffset6(modRM)
48 #define regFromModRM(modRM) threeBitsFromOffset3(modRM)
49 #define rmFromModRM(modRM) threeBitsFromOffset0(modRM)
51 #define scaleFromSIB(sib) twoBitsFromOffset6(sib)
52 #define indexFromSIB(sib) threeBitsFromOffset3(sib)
53 #define baseFromSIB(sib) threeBitsFromOffset0(sib)
55 #define wFromREX(rex) bitFromOffset3(rex)
56 #define rFromREX(rex) bitFromOffset2(rex)
57 #define xFromREX(rex) bitFromOffset1(rex)
58 #define bFromREX(rex) bitFromOffset0(rex)
60 #define mFromREX2(rex2) bitFromOffset7(rex2)
61 #define r2FromREX2(rex2) bitFromOffset6(rex2)
62 #define x2FromREX2(rex2) bitFromOffset5(rex2)
63 #define b2FromREX2(rex2) bitFromOffset4(rex2)
64 #define wFromREX2(rex2) bitFromOffset3(rex2)
65 #define rFromREX2(rex2) bitFromOffset2(rex2)
66 #define xFromREX2(rex2) bitFromOffset1(rex2)
67 #define bFromREX2(rex2) bitFromOffset0(rex2)
69 #define rFromXOP2of3(xop) invertedBitFromOffset7(xop)
70 #define xFromXOP2of3(xop) invertedBitFromOffset6(xop)
71 #define bFromXOP2of3(xop) invertedBitFromOffset5(xop)
72 #define mmmmmFromXOP2of3(xop) fiveBitsFromOffset0(xop)
73 #define wFromXOP3of3(xop) bitFromOffset7(xop)
74 #define vvvvFromXOP3of3(xop) invertedFourBitsFromOffset3(xop)
75 #define lFromXOP3of3(xop) bitFromOffset2(xop)
76 #define ppFromXOP3of3(xop) twoBitsFromOffset0(xop)
78 #define rFromVEX2of2(vex) invertedBitFromOffset7(vex)
79 #define vvvvFromVEX2of2(vex) invertedFourBitsFromOffset3(vex)
80 #define lFromVEX2of2(vex) bitFromOffset2(vex)
81 #define ppFromVEX2of2(vex) twoBitsFromOffset0(vex)
83 #define rFromVEX2of3(vex) invertedBitFromOffset7(vex)
84 #define xFromVEX2of3(vex) invertedBitFromOffset6(vex)
85 #define bFromVEX2of3(vex) invertedBitFromOffset5(vex)
86 #define mmmmmFromVEX2of3(vex) fiveBitsFromOffset0(vex)
87 #define wFromVEX3of3(vex) bitFromOffset7(vex)
88 #define vvvvFromVEX3of3(vex) invertedFourBitsFromOffset3(vex)
89 #define lFromVEX3of3(vex) bitFromOffset2(vex)
90 #define ppFromVEX3of3(vex) twoBitsFromOffset0(vex)
92 #define rFromEVEX2of4(evex) invertedBitFromOffset7(evex)
93 #define xFromEVEX2of4(evex) invertedBitFromOffset6(evex)
94 #define bFromEVEX2of4(evex) invertedBitFromOffset5(evex)
95 #define r2FromEVEX2of4(evex) invertedBitFromOffset4(evex)
96 #define b2FromEVEX2of4(evex) bitFromOffset3(evex)
97 #define mmmFromEVEX2of4(evex) threeBitsFromOffset0(evex)
98 #define wFromEVEX3of4(evex) bitFromOffset7(evex)
99 #define vvvvFromEVEX3of4(evex) invertedFourBitsFromOffset3(evex)
100 #define uFromEVEX3of4(evex) invertedBitFromOffset2(evex)
101 #define ppFromEVEX3of4(evex) twoBitsFromOffset0(evex)
102 #define oszcFromEVEX3of4(evex) fourBitsFromOffset3(evex)
103 #define zFromEVEX4of4(evex) bitFromOffset7(evex)
104 #define l2FromEVEX4of4(evex) bitFromOffset6(evex)
105 #define lFromEVEX4of4(evex) bitFromOffset5(evex)
106 #define bFromEVEX4of4(evex) bitFromOffset4(evex)
107 #define v2FromEVEX4of4(evex) invertedBitFromOffset3(evex)
108 #define aaaFromEVEX4of4(evex) threeBitsFromOffset0(evex)
109 #define nfFromEVEX4of4(evex) bitFromOffset2(evex)
110 #define scFromEVEX4of4(evex) fourBitsFromOffset0(evex)
112// These enums represent Intel registers for use by the decoder.
151 #define EA_BASES_16BIT \
219 #define EA_BASES_32BIT \
287 #define EA_BASES_64BIT \
477 #define REGS_MASK_PAIRS \
483 #define REGS_SEGMENT \
509 #define REGS_CONTROL \
538 #define ALL_EA_BASES \
543 #define ALL_SIB_BASES \
564/// All possible values of the base field for effective-address
565/// computations, a.k.a. the Mod and R/M fields of the ModR/M byte.
566/// We distinguish between bases (EA_BASE_*) and registers that just happen
567/// to be referred to when Mod == 0b11 (EA_REG_*).
571 #define ENTRY(x) EA_BASE_##x,
574#define ENTRY(x) EA_REG_##x,
581/// All possible values of the SIB index field.
582/// borrows entries from ALL_EA_BASES with the special case that
583/// sib is synonymous with NONE.
584/// Vector SIB: index can be XMM or YMM.
588#define ENTRY(x) SIB_INDEX_##x,
598/// All possible values of the SIB base field.
602#define ENTRY(x) SIB_BASE_##x,
609/// Possible displacement types for effective-address computations.
612/// All possible values of the reg field in the ModR/M byte.
615#define ENTRY(x) MODRM_REG_##x,
622/// All possible segment overrides.
634/// Possible values for the VEX.m-mmmm field
651/// Possible values for the VEX.pp/EVEX.pp field
667/// The specification for how to extract and interpret a full instruction and
673/// The x86 internal instruction, which is produced by the decoder.
675 // Opaque value passed to the reader
677 // The address of the next byte to read via the reader
680 // General instruction information
682 // The mode to disassemble for (64-bit, protected, real)
684 // The start of the instruction, usable with the reader
686 // The length of the instruction, in bytes
691 // The possible mandatory prefix
693 // The value of the vector extension prefix(EVEX/VEX/XOP), if present
695 // The type of the vector extension prefix
697 // The value of the REX2 prefix, if present
699 // The value of the REX prefix, if present
701 // The segment override type
703 // 1 if the prefix byte, 0xf2 or 0xf3 is xacquire or xrelease
706 // Address-size override
708 // Operand-size override
712 // The repeat prefix if any
715 // Sizes of various critical pieces of data, in bytes
721 // Offsets from the start of the instruction to the pieces of data, which is
722 // needed to find relocation entries for adding symbolic operands.
728 // The last byte of the opcode, not counting any ModR/M extension
733 // The type of opcode, used for indexing into the array of decode tables
735 // The instruction ID, extracted from the decode table
737 // The specifier for the instruction, from the instruction info table
740 // state for additional bytes, consumed during operand decode. Pattern:
741 // consumed___ indicates that the byte was already consumed and does not
742 // need to be consumed again.
744 // The VEX.vvvv field, which contains a third register operand for some AVX
748 // The writemask for AVX-512 instructions which is contained in EVEX.aaa
751 // The ModR/M byte, which contains most register operands and some portion of
752 // all memory operands.
756 // The SIB byte, used for more complex 32- or 64-bit memory operands
759 // The displacement, used for memory operands
762 // Immediates. There can be three in some cases
767 // A register or immediate operand encoded into the opcode
770 // Portions of the ModR/M byte
772 // These fields determine the allowable values for the ModR/M fields, which
773 // depend on operand and address widths.
777 // The Mod and R/M fields can encode a base for an effective address, or a
778 // register. These are separated into two fields here.
781 // The reg field always encodes a register
790 // Embedded rounding control.
796}
// namespace X86Disassembler
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
EABase
All possible values of the base field for effective-address computations, a.k.a.
VEXLeadingOpcodeByte
Possible values for the VEX.m-mmmm field.
Reg
All possible values of the reg field in the ModR/M byte.
DisassemblerMode
Decoding mode for the Intel disassembler.
SIBBase
All possible values of the SIB base field.
VEXPrefixCode
Possible values for the VEX.pp/EVEX.pp field.
EADisplacement
Possible displacement types for effective-address computations.
SIBIndex
All possible values of the SIB index field.
SegmentOverride
All possible segment overrides.
This is an optimization pass for GlobalISel generic memory operations.
The specification for how to extract and interpret a full instruction and its operands.
The x86 internal instruction, which is produced by the decoder.
ArrayRef< OperandSpecifier > operands
EADisplacement eaDisplacement
uint8_t rex2ExtensionPrefix[2]
uint8_t vectorExtensionPrefix[4]
SegmentOverride segmentOverride
uint8_t numImmediatesConsumed
llvm::ArrayRef< uint8_t > bytes
uint8_t numImmediatesTranslated
const InstructionSpecifier * spec
VectorExtensionType vectorExtensionType
uint8_t displacementOffset