1//===- llvm/CodeGen/GlobalISel/GIMatchTableExecutor.cpp -------------------===// 
  3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 
  4// See https://llvm.org/LICENSE.txt for license information. 
  5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 
  7//===----------------------------------------------------------------------===// 
  10/// This file implements the GIMatchTableExecutor class. 
  12//===----------------------------------------------------------------------===// 
  20 #define DEBUG_TYPE "gi-match-table-executor" 
  35 return VRegVal->Value.getSExtValue() == 
Value;
 
  39 return VRegVal->getSExtValue() == 
Value;
 
 
  51 if (RootI->
getOpcode() != TargetOpcode::G_PTR_ADD)
 
  56 if (RHSI->
getOpcode() != TargetOpcode::G_CONSTANT)
 
 
  66 // Immediate neighbours are already folded. 
  68 std::next(
MI.getIterator()) == IntoMIIter)
 
  71 // Convergent instructions cannot be moved in the CFG. 
  72 if (
MI.isConvergent() && 
MI.getParent() != IntoMI.
getParent())
 
  75 if (
MI.isLoadFoldBarrier())
 
  78 // If the load is simple, check instructions between MI and IntoMI 
  80 if (
MI.memoperands_empty())
 
  82 auto &MMO = **(
MI.memoperands_begin());
 
  83 if (MMO.isAtomic() || MMO.isVolatile())
 
  86 // Ensure instructions between MI and IntoMI are not affected when combined 
  88 const unsigned MaxIter = 20;
 
  91 if (CurrMI.isLoadFoldBarrier())
 
  94 if (Iter++ == MaxIter)
 
  101 return !
MI.mayLoad();
 
 
unsigned const MachineRegisterInfo * MRI
 
LLVM_ABI GIMatchTableExecutor()
 
LLVM_ABI bool isBaseWithConstantOffset(const MachineOperand &Root, const MachineRegisterInfo &MRI) const
Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on the right-hand side.
 
LLVM_ABI bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI, bool Splat=false) const
 
LLVM_ABI bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const
Return true if MI can obviously be folded into IntoMI.
 
Representation of each machine instruction.
 
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
 
const MachineBasicBlock * getParent() const
 
const MachineOperand & getOperand(unsigned i) const
 
MachineOperand class - Representation of each machine instruction operand.
 
bool isReg() const
isReg - Tests if this is a MO_Register operand.
 
Register getReg() const
getReg - Returns the register number.
 
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
 
LLVM Value Representation.
 
self_iterator getIterator()
 
This is an optimization pass for GlobalISel generic memory operations.
 
LLVM_ABI std::optional< APInt > getIConstantSplatVal(const Register Reg, const MachineRegisterInfo &MRI)
 
auto instructionsWithoutDebug(IterT It, IterT End, bool SkipPseudoOp=true)
Construct a range iterator which begins at It and moves forwards until End is reached,...
 
LLVM_ABI std::optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
 
LLVM_ABI MatcherState(unsigned MaxRenderers)
 
std::vector< ComplexRendererFns::value_type > Renderers