Sorry I wasn't clear.

I meant:

[24bit signal][8 bits padding] for a total of 32 bits per sample. (This is to interface with some annoying DSPs).

This is what i ended up with:

 size_t readBytes(uint8_t *data, size_t size) override {
 if (p_stream==nullptr) return 0;
 size_t samples = size / sizeof(TTo);
 TTo *data_target = (TTo *)data;
 TFrom source;
 for (size_t j=0;j<samples;j++){
 source = 0;
 p_stream->readBytes((uint8_t*)&source, sizeof(TFrom));
 data_target[j]= ((int32_t) source) << 8;;
 }
 return size;
 }

But I get very weird results when piping this to I2S. (the zero padding doesn't seem to be at the end of each word. I paste the output of my logic analyzer if that can help.

Thanks a lot!

The Duty cycle and frequency is correct, it's just that there seem to be a random phase shift. Is there something that needs to be done when piping A2DP to I2S to synchronize them maybe ?

What is the datatype of source ?

Are you sure that you do something with the data_target. To me it looks as if you output the input data.

In my second example I just do this:

 data_target[j] = -1;
 data_target[j]= data_target[j] << 8;

So I don't think the problem is with the source

My gut feeling point me towards an alignment issue between the data and the LRCLK signal.

Unfortunately the shift is different at every reboot and I have to follow the I2S format of the DSP I'm using. I think I got something to work with the basic A2DP API though !