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1 | 1 | # Dynamic pattern detector using verilog |
2 | 2 | A project to implement dynamic pattern detector using verilog in different ways. |
3 | | -- Dynamic pattern detector with variable number of bits in implicit style fsm which supports APB protocol to configure pattern register value. |
| 3 | +- Dynamic pattern detector with variable number of bits in implicit style fsm which supports APB protocol to configure pattern register value. (COMING SOON) |
4 | 4 | - Dynamic 3 bit pattern detector in explicit style fsm. |
5 | 5 | - Dynamic pattern detector with variable number of bits in implicit style fsm. |
6 | 6 |
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