Skip to content

Navigation Menu

Sign in
Appearance settings

Search code, repositories, users, issues, pull requests...

Provide feedback

We read every piece of feedback, and take your input very seriously.

Saved searches

Use saved searches to filter your results more quickly
Sign up
Appearance settings

Commit 0d58748

Browse files
author
robert
committed
Add STM32N driver support
1 parent 2c5a6d4 commit 0d58748

File tree

4 files changed

+44
-24
lines changed

4 files changed

+44
-24
lines changed

‎mongoose.c‎

Lines changed: 18 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -24230,9 +24230,10 @@ struct mg_tcpip_driver mg_tcpip_driver_stm32f = {
2423024230
#endif
2423124231

2423224232

24233-
#if MG_ENABLE_TCPIP && (MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN)
24233+
#if MG_ENABLE_TCPIP && (MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN || \
24234+
MG_ENABLE_DRIVER_STM32N)
2423424235
// STM32H: vendor modded single-queue Synopsys v4.2
24235-
// MCXNx4x: dual-queue Synopsys v5.2 with no hash table option
24236+
// STM32N, MCXNx4x: dual-queue Synopsys v5.2 with no hash table option
2423624237
// RT1170 ENET_QOS: quad-queue Synopsys v5.1
2423724238
struct synopsys_enet_qos {
2423824239
volatile uint32_t MACCR, MACECR, MACPFR, MACWTR, MACHT0R, MACHT1R,
@@ -24271,17 +24272,20 @@ struct synopsys_enet_qos {
2427124272
0x8000UL))
2427224273
#elif MG_ENABLE_DRIVER_MCXN
2427324274
#define ETH ((struct synopsys_enet_qos *) (uintptr_t) 0x40100000UL)
24275+
#elif MG_ENABLE_DRIVER_STM32N
24276+
#define ETH ((struct synopsys_enet_qos *) (uintptr_t) 0x48036000UL)
2427424277
#endif
2427524278

2427624279
#define ETH_PKT_SIZE 1540 // Max frame size
2427724280
#define ETH_DESC_CNT 4 // Descriptors count
2427824281
#define ETH_DS 4 // Descriptor size (words)
2427924282

24280-
static volatile uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS]; // RX descriptors
24281-
static volatile uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS]; // TX descriptors
24282-
static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // RX ethernet buffers
24283-
static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // TX ethernet buffers
24284-
static struct mg_tcpip_if *s_ifp; // MIP interface
24283+
#define MG_8BYTE_ALIGNED __attribute__((aligned(8)))
24284+
static volatile uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS] MG_8BYTE_ALIGNED;
24285+
static volatile uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS] MG_8BYTE_ALIGNED;
24286+
static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_8BYTE_ALIGNED;
24287+
static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_8BYTE_ALIGNED;
24288+
static struct mg_tcpip_if *s_ifp; // MIP interface
2428524289

2428624290
static uint16_t eth_read_phy(uint8_t addr, uint8_t reg) {
2428724291
ETH->MACMDIOAR &= (0xF << 8);
@@ -24332,7 +24336,7 @@ static bool mg_tcpip_driver_stm32h_init(struct mg_tcpip_if *ifp) {
2433224336
ETH->DMASBMR |= MG_BIT(12); // AAL NOTE(scaprile): is this actually needed
2433324337
ETH->MACIER = 0; // Do not enable additional irq sources (reset value)
2433424338
ETH->MACTFCR = MG_BIT(7); // Disable zero-quanta pause
24335-
#if !MG_ENABLE_DRIVER_MCXN
24339+
#if MG_ENABLE_DRIVER_STM32H
2433624340
ETH->MACPFR = MG_BIT(10); // Perfect filtering
2433724341
#endif
2433824342
struct mg_phy phy = {eth_read_phy, eth_write_phy};
@@ -24401,7 +24405,7 @@ static size_t mg_tcpip_driver_stm32h_tx(const void *buf, size_t len,
2440124405
}
2440224406

2440324407
static void mg_tcpip_driver_stm32h_update_hash_table(struct mg_tcpip_if *ifp) {
24404-
#if MG_ENABLE_DRIVER_MCXN
24408+
#if MG_ENABLE_DRIVER_MCXN || MG_ENABLE_DRIVER_STM32N
2440524409
ETH->MACPFR = MG_BIT(4); // Pass Multicast (pass all multicast frames)
2440624410
#else
2440724411
// TODO(): read database, rebuild hash table
@@ -24412,7 +24416,7 @@ static void mg_tcpip_driver_stm32h_update_hash_table(struct mg_tcpip_if *ifp) {
2441224416
ETH->MACA1HR = (uint32_t) mcast_addr[5] << 8 | (uint32_t) mcast_addr[4];
2441324417
ETH->MACA1HR |= MG_BIT(31); // AE
2441424418
#endif
24415-
(void) ifp;
24419+
(void) ifp;
2441624420
}
2441724421

2441824422
static bool mg_tcpip_driver_stm32h_poll(struct mg_tcpip_if *ifp, bool s1) {
@@ -24446,9 +24450,12 @@ static uint32_t s_rxno;
2444624450
#if MG_ENABLE_DRIVER_MCXN
2444724451
void ETHERNET_IRQHandler(void);
2444824452
void ETHERNET_IRQHandler(void) {
24449-
#else
24453+
#elif MG_ENABLE_DRIVER_STM32H
2445024454
void ETH_IRQHandler(void);
2445124455
void ETH_IRQHandler(void) {
24456+
#else
24457+
void ETH1_IRQHandler(void);
24458+
void ETH1_IRQHandler(void) {
2445224459
#endif
2445324460
if (ETH->DMACSR & MG_BIT(6)) { // Frame received, loop
2445424461
ETH->DMACSR = MG_BIT(15) | MG_BIT(6); // Clear flag

‎mongoose.h‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3596,7 +3596,10 @@ struct mg_tcpip_driver_stm32f_data {
35963596
#if !defined(MG_ENABLE_DRIVER_MCXN)
35973597
#define MG_ENABLE_DRIVER_MCXN 0
35983598
#endif
3599-
#if MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN
3599+
#if !defined(MG_ENABLE_DRIVER_STM32N)
3600+
#define MG_ENABLE_DRIVER_STM32N 0
3601+
#endif
3602+
#if MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN || MG_ENABLE_DRIVER_STM32N
36003603

36013604
struct mg_tcpip_driver_stm32h_data {
36023605
// MDC clock divider. MDC clock is derived from HCLK, must not exceed 2.5MHz

‎src/drivers/stm32h.c‎

Lines changed: 18 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,9 @@
11
#include "net_builtin.h"
22

3-
#if MG_ENABLE_TCPIP && (MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN)
3+
#if MG_ENABLE_TCPIP && (MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN || \
4+
MG_ENABLE_DRIVER_STM32N)
45
// STM32H: vendor modded single-queue Synopsys v4.2
5-
// MCXNx4x: dual-queue Synopsys v5.2 with no hash table option
6+
// STM32N, MCXNx4x: dual-queue Synopsys v5.2 with no hash table option
67
// RT1170 ENET_QOS: quad-queue Synopsys v5.1
78
struct synopsys_enet_qos {
89
volatile uint32_t MACCR, MACECR, MACPFR, MACWTR, MACHT0R, MACHT1R,
@@ -41,17 +42,20 @@ struct synopsys_enet_qos {
4142
0x8000UL))
4243
#elif MG_ENABLE_DRIVER_MCXN
4344
#define ETH ((struct synopsys_enet_qos *) (uintptr_t) 0x40100000UL)
45+
#elif MG_ENABLE_DRIVER_STM32N
46+
#define ETH ((struct synopsys_enet_qos *) (uintptr_t) 0x48036000UL)
4447
#endif
4548

4649
#define ETH_PKT_SIZE 1540 // Max frame size
4750
#define ETH_DESC_CNT 4 // Descriptors count
4851
#define ETH_DS 4 // Descriptor size (words)
4952

50-
static volatile uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS]; // RX descriptors
51-
static volatile uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS]; // TX descriptors
52-
static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // RX ethernet buffers
53-
static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // TX ethernet buffers
54-
static struct mg_tcpip_if *s_ifp; // MIP interface
53+
#define MG_8BYTE_ALIGNED __attribute__((aligned(8)))
54+
static volatile uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS] MG_8BYTE_ALIGNED;
55+
static volatile uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS] MG_8BYTE_ALIGNED;
56+
static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_8BYTE_ALIGNED;
57+
static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_8BYTE_ALIGNED;
58+
static struct mg_tcpip_if *s_ifp; // MIP interface
5559

5660
static uint16_t eth_read_phy(uint8_t addr, uint8_t reg) {
5761
ETH->MACMDIOAR &= (0xF << 8);
@@ -102,7 +106,7 @@ static bool mg_tcpip_driver_stm32h_init(struct mg_tcpip_if *ifp) {
102106
ETH->DMASBMR |= MG_BIT(12); // AAL NOTE(scaprile): is this actually needed
103107
ETH->MACIER = 0; // Do not enable additional irq sources (reset value)
104108
ETH->MACTFCR = MG_BIT(7); // Disable zero-quanta pause
105-
#if !MG_ENABLE_DRIVER_MCXN
109+
#if MG_ENABLE_DRIVER_STM32H
106110
ETH->MACPFR = MG_BIT(10); // Perfect filtering
107111
#endif
108112
struct mg_phy phy = {eth_read_phy, eth_write_phy};
@@ -171,7 +175,7 @@ static size_t mg_tcpip_driver_stm32h_tx(const void *buf, size_t len,
171175
}
172176

173177
static void mg_tcpip_driver_stm32h_update_hash_table(struct mg_tcpip_if *ifp) {
174-
#if MG_ENABLE_DRIVER_MCXN
178+
#if MG_ENABLE_DRIVER_MCXN||MG_ENABLE_DRIVER_STM32N
175179
ETH->MACPFR = MG_BIT(4); // Pass Multicast (pass all multicast frames)
176180
#else
177181
// TODO(): read database, rebuild hash table
@@ -182,7 +186,7 @@ static void mg_tcpip_driver_stm32h_update_hash_table(struct mg_tcpip_if *ifp) {
182186
ETH->MACA1HR = (uint32_t) mcast_addr[5] << 8 | (uint32_t) mcast_addr[4];
183187
ETH->MACA1HR |= MG_BIT(31); // AE
184188
#endif
185-
(void) ifp;
189+
(void) ifp;
186190
}
187191

188192
static bool mg_tcpip_driver_stm32h_poll(struct mg_tcpip_if *ifp, bool s1) {
@@ -216,9 +220,12 @@ static uint32_t s_rxno;
216220
#if MG_ENABLE_DRIVER_MCXN
217221
void ETHERNET_IRQHandler(void);
218222
void ETHERNET_IRQHandler(void) {
219-
#else
223+
#elif MG_ENABLE_DRIVER_STM32H
220224
void ETH_IRQHandler(void);
221225
void ETH_IRQHandler(void) {
226+
#else
227+
void ETH1_IRQHandler(void);
228+
void ETH1_IRQHandler(void) {
222229
#endif
223230
if (ETH->DMACSR & MG_BIT(6)) { // Frame received, loop
224231
ETH->DMACSR = MG_BIT(15) | MG_BIT(6); // Clear flag

‎src/drivers/stm32h.h‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,10 @@
77
#if !defined(MG_ENABLE_DRIVER_MCXN)
88
#define MG_ENABLE_DRIVER_MCXN 0
99
#endif
10-
#if MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN
10+
#if !defined(MG_ENABLE_DRIVER_STM32N)
11+
#define MG_ENABLE_DRIVER_STM32N 0
12+
#endif
13+
#if MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN || MG_ENABLE_DRIVER_STM32N
1114

1215
struct mg_tcpip_driver_stm32h_data {
1316
// MDC clock divider. MDC clock is derived from HCLK, must not exceed 2.5MHz

0 commit comments

Comments
(0)

AltStyle によって変換されたページ (->オリジナル) /