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This repository was archived by the owner on Nov 26, 2020. It is now read-only.

Commit bfe2f82

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vcd dump and monitor statement added
1 parent d8b5292 commit bfe2f82

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1 file changed

+26
-20
lines changed

1 file changed

+26
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‎src/FourBitCounter.v‎

Lines changed: 26 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
1+
// An active low reset signal is used for resetting the counter.
12
module counter (input clk, input rstn, output reg[3:0] out);
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always @ (posedge clk) begin
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if (! rstn)
@@ -8,26 +9,31 @@ module counter (input clk, input rstn, output reg[3:0] out);
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endmodule
910

1011
module tb_counter;
11-
reg clk;
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reg rstn;
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wire [3:0] out;
12+
reg clk;
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reg rstn;
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wire [3:0] out;
1415

15-
counter c0 ( .clk (clk),
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.rstn (rstn),
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.out (out));
18-
19-
// Generate a clock that should be driven to design
20-
// This clock will flip its value every 5ns -> time period = 10ns -> freq = 100 MHz
21-
always #5 clk = ~clk;
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23-
initial begin
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clk <= 0;
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rstn <= 0;
26-
27-
#20 rstn <= 1;
28-
#80 rstn <= 0;
29-
#50 rstn <= 1;
16+
counter c0(.clk(clk), .rstn (rstn), .out (out));
17+
18+
// Generate a clock that should be driven to design
19+
// This clock will flip its value every 5ns -> time period = 10ns -> freq = 100 MHz
20+
always #5 clk = ~clk;
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initial
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begin
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$dumpfile("vcd/FourBitCounter.vcd");
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$dumpvars(0,tb_counter);
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$display("Clock \t Reset \t Output");
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$monitor("%b %b %b", clk, rstn, out);
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clk <= 0;
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rstn <= 0;
3032

31-
#20 $finish;
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end
33+
#20 rstn <= 1;
34+
#80 rstn <= 0;
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#50 rstn <= 1;
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#20
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$finish;
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end
3339
endmodule

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