1+ import re
2+ 3+ f = open ("IntermediateCode.txt" , 'r' )
4+ lines = f .readlines ()
5+ f .close ()
6+ 7+ fifo_return_reg = 'R0'
8+ 9+ reg = [0 ]* 13
10+ var = {} # {'a': 'R0', '1':'R0'}
11+ store_seq = []
12+ fifo_reg = 0
13+ operator_list = {'+' :'ADD' , '-' :'SUB' , '*' :'MUL' , '/' :'DIV' , '==' :'E' , '!=' :'NE' , '>' :'G' , '<' :'L' , '>=' :'GE' ,'<=' :'LE' ,'and' :'AND' ,'or' :'OR' }
14+ 15+ ################################################################
16+ def fifo ():
17+ # print(" In FIFO Function", var)
18+ # print("\n\n Store seq", store_seq)
19+ global fifo_reg
20+ global fifo_return_reg
21+ for k ,v in var .copy ().items ():
22+ if (v == 'R' + str (fifo_reg )):
23+ fifo_return_reg = v
24+ # print("K", k)
25+ # print("V", v)
26+ var .pop (k )
27+ if (k in store_seq ):
28+ store_seq .remove (k )
29+ print ("ST " , k , ', ' , v , sep = '' )
30+ fifo_reg = int (fifo_return_reg [1 :]) + 1
31+ # print("FIFO reg & v", fifo_reg, fifo_return_reg)
32+ return fifo_return_reg
33+ ###################################################################
34+ def getreg ():
35+ for i in range (0 ,13 ):
36+ if reg [i ]== 0 :
37+ reg [i ]= 1
38+ return 'R' + str (i )
39+ register = fifo ()
40+ # print("REGISTER" , register)
41+ return register
42+ ################################################################
43+ for line in lines :
44+ line = line .strip ()
45+ line = line .strip ('\n ' )
46+ line = line .split ()
47+ length = len (line )
48+ ###############################################################
49+ #branch
50+ #L0:
51+ if (length == 1 ):
52+ print (line [0 ])
53+ ###############################################################
54+ # temporary variables
55+ # ignore statement
56+ # re.findall('^t[0-9]+$')
57+ elif (re .findall ('^t[0-9]+$' , line [0 ])):
58+ continue
59+ ###########################################################
60+ # goto
61+ #simple assignment
62+ #a = b
63+ #LD Rn, b
64+ elif (length == 3 ):
65+ lhs = line [0 ]
66+ operand = line [2 ]
67+ if operand not in var :
68+ var [operand ] = getreg ()
69+ if (operand .isalpha ()):
70+ print ("LD " , var [operand ], ', ' , operand , sep = '' )
71+ else :
72+ print ("MOV " , var [operand ], ', #' , operand , sep = '' )
73+ #remove the old occurence and put new one -->
74+ if lhs in store_seq :
75+ old_reg = var [lhs ]
76+ index = store_seq .index (lhs )
77+ store_seq .pop (index )
78+ var [lhs ] = var [operand ]
79+ if (old_reg not in var .values ()):
80+ reg [int (old_reg [1 :])] = 0
81+ else :
82+ var [lhs ] = var [operand ]
83+ store_seq .append (lhs )
84+ ###################################################
85+ elif ('goto' in line ):
86+ # if x goto l
87+ if ('if' in line ):
88+ operand = line [1 ]
89+ label = line [3 ]
90+ if operand not in var :
91+ var [operand ] = getreg ()
92+ if (operand .isalpha ()):
93+ print ("LD " , var [operand ], ', ' , operand , sep = '' )
94+ else :
95+ print ("MOV " , var [operand ], ', #' , operand , sep = '' )
96+ print ("BNEZ " , var [operand ], ', ' , label , sep = '' )
97+ # goto l
98+ else :
99+ print ("BR" ,line [1 ])
100+ ###############################################################
101+ # assignment expressions
102+ # +, -, *, /, >, <, <=, >=, ==, !=, not, and, or
103+ #a = b + c
104+ else :
105+ if (len (line )== 5 ):
106+ oper = line [3 ]
107+ operand1 = line [2 ]
108+ operand2 = line [4 ]
109+ lhs = line [0 ]
110+ if operand1 not in var :
111+ var [operand1 ] = getreg ()
112+ if (operand1 .isalpha ()):
113+ print ("LD " , var [operand1 ], ', ' , operand1 , sep = '' )
114+ else :
115+ print ("MOV " , var [operand1 ], ', #' , operand1 , sep = '' )
116+ if operand2 not in var :
117+ var [operand2 ] = getreg ()
118+ if (operand2 .isalpha ()):
119+ print ("LD " , var [operand2 ], ', ' , operand2 , sep = '' )
120+ else :
121+ print ("MOV " , var [operand2 ], ', #' , operand2 , sep = '' )
122+ operator_print = operator_list [oper ]
123+ #remove the old occurence and put new one -->
124+ if lhs in store_seq :
125+ old_reg = var [lhs ]
126+ index = store_seq .index (lhs )
127+ store_seq .pop (index )
128+ var [lhs ] = getreg ()
129+ reg [int (old_reg [1 :])] = 0
130+ else :
131+ var [lhs ] = getreg ()
132+ store_seq .append (lhs )
133+ print (operator_print , ' ' , var [lhs ], ', ' , var [operand1 ], ', ' , var [operand2 ], sep = '' )
134+ else :
135+ operand = line [3 ]
136+ lhs = line [0 ]
137+ if operand not in var :
138+ var [operand ] = getreg ()
139+ if (operand .isalpha ()):
140+ print ("LD " , var [operand ], ', ' , operand , sep = '' )
141+ else :
142+ print ("MOV " , var [operand ], ', #' , operand , sep = '' )
143+ if lhs in store_seq :
144+ old_reg = var [lhs ]
145+ index = store_seq .index (lhs )
146+ store_seq .pop (index )
147+ var [lhs ] = getreg ()
148+ reg [int (old_reg [1 :])] = 0
149+ else :
150+ var [lhs ] = getreg ()
151+ store_seq .append (lhs )
152+ print ("NOT " , var [lhs ], ', ' , var [operand ], sep = '' )
153+ 154+ 155+ # store all variables
156+ for i in store_seq :
157+ print ("ST " , i , ', ' , var [i ], sep = '' )
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