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Commit 375a3a4

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ON-17007: handle ef10 truncation and CRC errors in the same way
1 parent e82edf1 commit 375a3a4

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3 files changed

+24
-5
lines changed

3 files changed

+24
-5
lines changed

‎src/lib/ciul/ef10_event.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,8 @@ typedef ci_qword_t ef_vi_event;
5858
ef_vi_inline unsigned discard_type(uint64_t error_bits)
5959
{
6060
const uint64_t l2_errors = ( (1llu << ESF_DZ_RX_ECC_ERR_LBN) |
61-
(1llu << ESF_DZ_RX_ECRC_ERR_LBN) );
61+
(1llu << ESF_DZ_RX_ECRC_ERR_LBN) |
62+
(1llu << ESF_DZ_RX_TRUNC_ERR_LBN) );
6263
const uint64_t l3_errors = ( (1llu << ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN) |
6364
(1llu << ESF_DZ_RX_IPCKSUM_ERR_LBN) );
6465

‎src/lib/ciul/ef10_vi.c‎

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -700,8 +700,12 @@ static int ef10_ef_vi_receive_set_discards(ef_vi* vi, unsigned discard_err_flags
700700
mask |= 1LL << ESF_DZ_RX_INNER_TCPUDP_CKSUM_ERR_LBN;
701701
if( discard_err_flags & EF_VI_DISCARD_RX_INNER_L3_CSUM_ERR )
702702
mask |= 1LL << ESF_DZ_RX_INNER_IPCKSUM_ERR_LBN;
703+
704+
#define FCS_DISCARD_BITS \
705+
((1LL << ESF_DZ_RX_ECRC_ERR_LBN) | (1LL << ESF_DZ_RX_TRUNC_ERR_LBN))
706+
703707
if( discard_err_flags & EF_VI_DISCARD_RX_ETH_FCS_ERR )
704-
mask |= 1LL << ESF_DZ_RX_ECRC_ERR_LBN;
708+
mask |= FCS_DISCARD_BITS;
705709

706710
vi->rx_discard_mask = CI_BSWAPC_LE64(mask);
707711
return 0;
@@ -723,7 +727,7 @@ static uint64_t ef10_ef_vi_receive_get_discards(ef_vi* vi)
723727
mask |= EF_VI_DISCARD_RX_INNER_L4_CSUM_ERR;
724728
if( vi_mask & 1LL << ESF_DZ_RX_INNER_IPCKSUM_ERR_LBN )
725729
mask |= EF_VI_DISCARD_RX_INNER_L3_CSUM_ERR;
726-
if( vi_mask & 1LL << ESF_DZ_RX_ECRC_ERR_LBN )
730+
if( vi_mask & FCS_DISCARD_BITS )
727731
mask |= EF_VI_DISCARD_RX_ETH_FCS_ERR;
728732

729733
return mask;
@@ -925,7 +929,7 @@ int ef10_vi_init(ef_vi* vi)
925929
| 1LL << ESF_DZ_RX_IPCKSUM_ERR_LBN
926930
| 1LL << ESF_DZ_RX_INNER_TCPUDP_CKSUM_ERR_LBN
927931
| 1LL << ESF_DZ_RX_INNER_IPCKSUM_ERR_LBN
928-
| 1LL << ESF_DZ_RX_ECRC_ERR_LBN);
932+
| FCS_DISCARD_BITS);
929933

930934
/* EF10 doesn't use phase bits in event queues */
931935
vi->evq_phase_bits = 0;

‎src/onload/distfiles/ReleaseNotes‎

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,12 @@ change.
5454
X4 Known Issues
5555
---------------
5656

57-
- CRC/Trunc error placeholder (need to confirm behaviour ON-17007)
57+
- The X4 enterprise datapath does not differentiate between CRC errors and
58+
truncation errors in RX discard events. As a result, these will be reported
59+
as EF_EVENT_RX_DISCARD_CRC_BAD in EF_EVENT_TYPE_RX_DISCARD for ef_vi users.
60+
This will be visible to onload users via the rx_discard_crc_bad statistic in
61+
stackdump. A side effect of this change is that truncation errors may be
62+
mischaracterised as CRC errors, including on older network cards.
5863

5964

6065
AMD Alveo(TM) X3 Series Low Latency Ethernet Adapter
@@ -212,4 +217,13 @@ is described and documented in the API functions:
212217
- ef_vi_for_each_tx_error_failed_transmit
213218

214219

220+
Change in behaviour for CRC and truncation RX discards
221+
------------------------------------------------------
222+
223+
To support X4, which is unable to differentiate between these error types in RX
224+
discard events, any NIC using the ef10 architecture, X2 or SFN8k, will also not
225+
differentiate between these error types. This only affects users with an MTU of
226+
larger than 1500.
227+
228+
215229
(c) Copyright 2025 Advanced Micro Devices, Inc.

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