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1 parent c36b43c commit ae3ceb0Copy full SHA for ae3ceb0
6-CS450/180-Cs450-counter-2bc.v
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+module top_module(
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+ input clk,
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+ input areset,
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+ input train_valid,
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+ input train_taken,
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+ output [1:0] state
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+);
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+
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+ //-------------Internal Constants-----------------
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+ parameter SNT=0, WNT=1, WT=2, ST=3 ; // states
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+ //-------------Internal Variables-----------------
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+ reg [1:0] next_state; //2 state bits for 4 states.
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+ // State transition logic - Combinational Logic
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+ always @(*) begin
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+ case(state)
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+ SNT : next_state = train_valid ? ( train_taken ? WNT : SNT ) : SNT ;
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+ WNT : next_state = train_valid ? ( train_taken ? WT : SNT ) : WNT ;
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+ WT : next_state = train_valid ? ( train_taken ? ST : WNT ) : WT ;
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+ ST : next_state = train_valid ? ( train_taken ? ST : WT ) : ST ;
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+ endcase
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+ end
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+ always @(posedge clk, posedge areset) begin
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+ // State flip-flops with asynchronous reset
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+ if(areset)
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+ state <= WNT ;
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+ else
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+ state <= next_state;
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+endmodule
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