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Commit 14bc842

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Build a circuit from a simulation waveform solved
1 parent e2f60c3 commit 14bc842

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9 files changed

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module top_module (
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input a,
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input b,
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input c,
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input d,
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output q );//
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assign q = (a | b) & (c | d); //
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endmodule
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module top_module (
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input clk,
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input a,
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output q );
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always @(posedge clk)
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q <= ~a;
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endmodule

‎4-Verification-Reading Simulations/17-Build a circuit from a simulation waveform/170-Sequential-circuit7.v‎

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module top_module (
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input clock,
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input a,
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output p,
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output q );
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always @(*)
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if(clock)
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p = a;
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always @(negedge clock)
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q <= a;
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endmodule

‎4-Verification-Reading Simulations/17-Build a circuit from a simulation waveform/171-Sequential-circuit8.v‎

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module top_module (
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input clk,
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input a,
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output [3:0] q );
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always @(posedge clk) begin
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if(a)
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q <= 4;
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else if( q == 6)
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q <= 0;
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else
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q <= q + 1;
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end
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endmodule

‎4-Verification-Reading Simulations/17-Build a circuit from a simulation waveform/172-Sequential-circuit9.v‎

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module top_module (
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input clk,
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input a,
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input b,
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output q,
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output state );
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assign q = a ^ b ^ state;
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always @(posedge clk) begin
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state <= a & b | b & state | a & state ;
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end
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endmodule

‎4-Verification-Reading Simulations/17-Build a circuit from a simulation waveform/173-Sequential-circuit10.v‎

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