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Commit 256da84

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Merge pull request #299 from JeffDeCola/develop
develop
2 parents e5e61ea + 80f1d45 commit 256da84

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13 files changed

+9
-17
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13 files changed

+9
-17
lines changed

‎README.md‎

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@@ -332,10 +332,6 @@ Where the testbench structure is,
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_A synchronous lifo using dual-port synchronous RAM._
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* [lifo_asynchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/lifo_asynchronous)
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_An asynchronous lifo using dual-port asynchronous RAM._
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* REGISTERS
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* [jeff_74x377](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/registers/jeff_74x377)

‎basic-code/sequential-logic/d_flip_flop_pos_edge_sync_en/README.md‎

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```text
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TEST START --------------------------------
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| TIME(ns) | EN | D | Q |
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---------------------------
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1 INIT | 15 | 1 | 0 | 0 |

‎basic-code/sequential-logic/d_flip_flop_pos_edge_sync_en/d_flip_flop_pos_edge_sync_en_tb.v‎

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@@ -58,7 +58,6 @@ module D_FLIP_FLOP_POS_EDGE_SYNC_EN_TB ();
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$display();
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$display("TEST START --------------------------------");
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$display();
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$display(" ");
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$display(" | TIME(ns) | EN | D | Q |");
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$display(" ---------------------------");
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// $monitor("%4d %10s | %8d | %d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, EN, D, Q_beh);

‎basic-code/sequential-logic/jk_flip_flop_pos_edge_sync_clear/README.md‎

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```text
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TEST START --------------------------------
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| TIME(ns) | CLRBAR | J | K | Q |
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-----------------------------------
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1 INIT | 22 | 1 | 0 | 0 | x |

‎basic-code/sequential-logic/jk_flip_flop_pos_edge_sync_clear/jk_flip_flop_pos_edge_sync_clear_tb.v‎

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$display();
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$display("TEST START --------------------------------");
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$display();
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$display(" ");
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$display(" | TIME(ns) | CLRBAR | J | K | Q |");
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$display(" -----------------------------------");
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// $monitor("%4d %10s | %8d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, CLRBAR, J, K, Q_beh);
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‎sequential-logic/memory/dual_port_ram_asynchronous/README.md‎

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if (we_A) begin
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mem[addr_A] <= data_in_A;
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data_out_A <= data_in_A;
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// READ
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// READ
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end else begin
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data_out_A <= mem[addr_A];
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end

‎sequential-logic/memory/dual_port_ram_asynchronous/dual_port_ram_asynchronous.v‎

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if (we_A) begin
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mem[addr_A] <= data_in_A;
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data_out_A <= data_in_A;
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// READ
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// READ
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end else begin
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data_out_A <= mem[addr_A];
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end

‎sequential-logic/memory/dual_port_ram_synchronous/README.md‎

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if (we_A) begin
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mem[addr_A] <= data_in_A;
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data_out_A <= data_in_A;
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// READ
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// READ
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end else begin
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data_out_A <= mem[addr_A];
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end

‎sequential-logic/memory/lifo_synchronous/README.md‎

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if (rst) begin
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wrt_ptr <= 4'b0000;
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rd_ptr <= 4'b0000;
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// BOTTOM - PUSH
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// BOTTOM - PUSH
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end else if ((wrt_ptr == 4'b0000) & (w_next)) begin
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wrt_ptr <= wrt_ptr + 1;
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// BOTTOM - POP
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end else if (w_next) begin
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wrt_ptr <= wrt_ptr + 1;
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rd_ptr <= rd_ptr + 1;
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// POP
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// POP
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end else if (r_next) begin
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wrt_ptr <= wrt_ptr - 1;
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rd_ptr <= rd_ptr - 1;

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