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.text
.global start
b start
delay:
	sub r7, r7, #1
	cmp r7, #0
	bne delay
	bx lr
status_led_toggle:
	ldr r0, =sio_base
	mov r1, #1
	lsl r1, r1, #25
	str r1, [r0, #0x1c]
	bx lr
start:
	ldr r0, =reset_base
	ldr r7, =atomic_set
	add r0, r0, r7
	// stuff to reset
	// bit 23 - UART1
	// bit 22 - UART0
	// bit 5 - SIO - IO_BANK0
	ldr r1, =0b10000000000000000100000
	str r1, [r0, #0]
	ldr r7, =0xf0000
	bl delay
	// Deassert the reset
	ldr r0, =reset_base
	mov r1, #0
	str r1, [r0, #0]
status_led_setup:
	// set GPIO25 to use sio - software control
	ldr r0, =io_bank
	mov r1, #5
	mov r7, #0xcc
	str r1, [r0, r7]
	// enable output
	ldr r0, =sio_base
	mov r1, #1
	lsl r1, r1, #25
	str r1, [r0, #0x24]
	// set output low
	str r1, [r0, #0x18]
uart:
	// set GPIO0 and GPIO1 to use uart0
	ldr r0, =io_bank
	mov r1, #2
	str r1, [r0, #0x4]
	str r1, [r0, #0xc]
	// Action list 4.2.7. Programmer's Model
	// enable Peripheral clock 2.15.3
	ldr r0, =clocks_base
	mov r1, #1
	lsl r1, r1, #11
	str r1, [r0, #0x48]
	ldr r0, =uart0_base
	// Set the baud rate divisors 4.2.3.2
	ldr r1, =813
	str r1, [r0, #0x24]
	mov r1, #51
	str r1, [r0, #0x28]
	// enable FIFOs bit 4
	// Set format bit 6:5
	// b11 = 8 bits; b10 = 7; bits b01 = 6 bits; b00 = 5 bits
	// Table 432. UARTLCR_H Register
	mov r1, #0b1110000
	str r1, [r0, #0x2c]
	// Enable FIFOs 4.2.8 Table 433 UARTCR Register
	ldr r1, =0b11000000001
	str r1, [r0, #0x30]
	// enable DREQ signals as in uart_init()
	mov r1, #0b11
	str r1, [r0, #0x48]
	bl status_led_toggle
// delay
	ldr r7, =0xf000
	bl delay
send:
	ldr r0, =uart0_base
	mov r1, #65
	str r1, [r0, #0]
	ldr r7, =0xf0000
	bl delay
	bl status_led_toggle
	b send
end:
	b end
	
.equ atomic_reset_base, 0x4000e000
.equ reset_base, 0x4000c000
.equ io_bank, 0x40014000
.equ sio_base, 0xd0000000
.equ pio0_base, 0x50200000
.equ pio1_base, 0x50300000
.equ clocks_base, 0x40008000
.equ uart0_base, 0x40034000
.equ atomic_xor, 0x1000
.equ atomic_set, 0x2000
.equ atomic_clear, 0x3000