irq_set_exclusive_handler(TIMER_IRQ_1, &DATA_ISR); 
 irq_set_enabled(TIMER_IRQ_1, true); // enables hw timer and NVIC entry for this core1

 #define TIMER_NUM 1
 #define TIMER_MASK (1<<TIMER_NUM)

 hw_set_bits(&timer_hw->intf, TIMER_MASK); // force trigger ISR on core1

 hw_clear_bits(&timer_hw->intf, TIMER_MASK); // disable in NVIC of core0

4.1.27.1. Detailed Description
RP2040 only has one tick generator, and it is part of the watchdog hardware.

TIMER_IRQ_0
....
TIMER_IRQ_3

4.1.28.1. Detailed Description

The timer has 4 alarms, and can output a separate interrupt for each alarm. The alarms match on the lower 32 bits of
the 64 bit counter which means they can be fired a maximum of 2^32 microseconds into the future. This is equivalent
to:
• 2^32 ÷ 10^6: ~4295 seconds
• 4295 ÷ 60: ~72 minutes
The timer is expected to be used for short sleeps, if you want a longer alarm see the hardware_rtc functions.

pie_face wrote: I know there are some utility fn in SDK which provide "alarms" and an alarm pool but I want find the doc on the processor.
The "4 alarms" do not appear to be part of the vocabulary of RP2040 manual. Neither is this anything to do with "sleeps", timers to not sleep the processor.
It seems there is some bleed over and confusion in this writing.
Where do I find the doc on the timing of these TIMER_IRQ_x events?

4.6. Timer
4.6.1. Overview
The system timer peripheral on RP2040 provides a global microsecond timebase for the system, and generates
interrupts based on this timebase. It supports the following features:
• A single 64-bit counter, incrementing once per microsecond
• This counter can be read from a pair of latching registers, for race-free reads over a 32-bit bus.
• Four alarms: match on the lower 32 bits of counter, IRQ on match.
...
4.6.3. Alarms
...
4.6.4. Programmer’s Model
... 4.6.4.4. Complete example using SDK
4.6.5. List of Registers