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15 posts • Page 1 of 1
max_verem
Posts: 6
Joined: Wed Sep 03, 2025 7:51 pm

drmModePageFlip with interlaced frame

Thu Sep 04, 2025 12:01 pm

I am working on interlaced PAL video playback on RPI4. Everything looks good but i cant understand which field (upper or lower) page_flip_handler belongs to.

Prototype of that function:

Code: Select all 

static void page_flip_handler(int fd, unsigned int frame,
 unsigned int sec, unsigned int usec, void *data)
has frame parameter which in my case is sequence of odd:
  • * ...
    * 278009
    * 278011
    * ...
or even:
  • * ...
    * 273372
    * 273374
    * ...
numbers, but none of them gives information about which field is displaying now.

I did a tests with two framebuffers. First has normal bars in upper fields and h-flipped bars in lower fields. Second has h-flipped bars in upper fields and normal bars in lower fields. So sequential displaying of that two framebuffer would produce either normal bars on CVBS output or horizontally flipped. it depends on initial phase which i trying to find (calculate) from frame parameter of page_flip_handler

may be somebody know how to get which field of interlaced frame is currently displaying or how to get scanout position from userspace?


i am using RPI4 with latest bookworm:

Code: Select all 

Linux rpi4 6.12.34+rpt-rpi-v8 #1 SMP PREEMPT Debian 1:6.12.34-1+rpt1~bookworm (2025年06月26日) aarch64 GNU/Linux
dom
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 8472
Joined: Wed Aug 17, 2011 7:41 pm

Re: drmModePageFlip with interlaced frame

Thu Sep 04, 2025 12:39 pm

On a pi5:

Code: Select all 

$ cat /sys/kernel/debug/dri/axi:gpu/hvs_regs | grep SCALER6D_DISP0_STATUS
 SCALER6D_DISP0_STATUS = 0x008c43e9
bit15 should show odd/even field.

On a Pi4:

Code: Select all 

$ cat /sys/kernel/debug/dri/gpu/hvs_regs | grep SCALER_DISPSTAT0
 SCALER_DISPSTAT0 = 0xa011c3bf
bit27 should show odd/even field.

The bit means:

Code: Select all 

1 = Current frame is the ODD field (lines 1, 3, 5, etc.).
0 = Current frame is the EVEN field (lines 0, 2, 4, etc.) or interlace mode is not enabled.
Now this is very hacky - 6by9 may have a better idea if this is available through DRM api.
6by9
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 18476
Joined: Wed Dec 04, 2013 11:27 am

Re: drmModePageFlip with interlaced frame

Thu Sep 04, 2025 3:29 pm

dom wrote: ↑
Thu Sep 04, 2025 12:39 pm
 Now this is very hacky - 6by9 may have a better idea if this is available through DRM api.
Not really. Most DRM devs considers interlacing as a dead technology. I don't think they even specify whether the page flips should happen at field or frame rate (part of the reason we had the discrepancy with Pi5/RP1 running at frame rate vs Pi0-4/vc4 being at field rate).

AIUI Scanout position is independent of interlacing - the HVS will read and generate all lines for the frame on every field, and then the pixel valve throws away the wrong lines for this field.

Within the kernel DRM APIs there is a get_scanout_position call, but I don't believe that gets exposed to userspace. It looks to only be used for timestamping vblank events.
Software Engineer at Raspberry Pi Ltd. Views expressed are still personal views.
I'm not interested in doing contracts for bespoke functionality - please don't ask.
6by9
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 18476
Joined: Wed Dec 04, 2013 11:27 am

Re: drmModePageFlip with interlaced frame

Thu Sep 04, 2025 3:31 pm

dom wrote: ↑
Thu Sep 04, 2025 12:39 pm
 On a pi5:

Code: Select all 

$ cat /sys/kernel/debug/dri/axi:gpu/hvs_regs | grep SCALER6D_DISP0_STATUS
 SCALER6D_DISP0_STATUS = 0x008c43e9
bit15 should show odd/even field.
Note that this will only be valid for HDMI producing interlaced output. The HVS isn't involved in the composite output on Pi5.
The register name also varies between the C1 and D0 stepping. Grepping for "_DISP0_STATUS" should give you the correct answer on either.
Software Engineer at Raspberry Pi Ltd. Views expressed are still personal views.
I'm not interested in doing contracts for bespoke functionality - please don't ask.
njh
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 600
Joined: Wed Aug 09, 2017 2:07 pm

Re: drmModePageFlip with interlaced frame

Fri Sep 05, 2025 9:41 am

6by9 wrote: ↑
Thu Sep 04, 2025 3:29 pm
 Not really. Most DRM devs considers interlacing as a dead technology. I don't think they even specify whether the page flips should happen at field or frame rate (part of the reason we had the discrepancy with Pi5/RP1 running at frame rate vs Pi0-4/vc4 being at field rate).
Just to confuse everyone: From the next OS release, the Pi5 Composite output will also be able to update at field rate. DPI has been able to do this for a while too. Although their drivers do "know" which field is being displayed, they have no way of telling anybody.
max_verem
Posts: 6
Joined: Wed Sep 03, 2025 7:51 pm

Re: drmModePageFlip with interlaced frame

Sat Sep 06, 2025 12:30 pm

Many thanks for info, but bit27 of SCALER_DISPSTAT0 is always zero in my case (RPI4, PAL CVBS output, kernel 6.12.34+rpt-rpi-v8).

I read SCALER_DISPSTAT0 on each page_flip_handler callback :

Code: Select all 

....
! [2025年09月06日 14:52:09.330] drm_output_current_field_rpi4:65: SCALER_DISPSTAT0=0x1020C000
! [2025年09月06日 14:52:09.350] drm_output_current_field_rpi4:65: SCALER_DISPSTAT0=0x10274000
! [2025年09月06日 14:52:09.370] drm_output_current_field_rpi4:65: SCALER_DISPSTAT0=0x1013C000
! [2025年09月06日 14:52:09.390] drm_output_current_field_rpi4:65: SCALER_DISPSTAT0=0x101A4000
! [2025年09月06日 14:52:09.410] drm_output_current_field_rpi4:65: SCALER_DISPSTAT0=0x1020C000
! [2025年09月06日 14:52:09.430] drm_output_current_field_rpi4:65: SCALER_DISPSTAT0=0x10274000
! [2025年09月06日 14:52:09.450] drm_output_current_field_rpi4:65: SCALER_DISPSTAT0=0x1013C000
! [2025年09月06日 14:52:09.470] drm_output_current_field_rpi4:65: SCALER_DISPSTAT0=0x101A4000
! [2025年09月06日 14:52:09.490] drm_output_current_field_rpi4:65: SCALER_DISPSTAT0=0x1020C000
! [2025年09月06日 14:52:09.510] drm_output_current_field_rpi4:65: SCALER_DISPSTAT0=0x10274000
! [2025年09月06日 14:52:09.530] drm_output_current_field_rpi4:65: SCALER_DISPSTAT0=0x1013C000
! [2025年09月06日 14:52:09.550] drm_output_current_field_rpi4:65: SCALER_DISPSTAT0=0x101A4000
....
and in bash loop (with 5 miliseconds delay):

Code: Select all 

....
 SCALER_DISPSTAT0 = 0x1020c000
 SCALER_DISPSTAT0 = 0x10274000
 SCALER_DISPSTAT0 = 0x10274000
 SCALER_DISPSTAT0 = 0x1013c000
 SCALER_DISPSTAT0 = 0x101a4000
 SCALER_DISPSTAT0 = 0x1020c000
 SCALER_DISPSTAT0 = 0x1020c000
 SCALER_DISPSTAT0 = 0x10274000
 SCALER_DISPSTAT0 = 0x1013c000
 SCALER_DISPSTAT0 = 0x101a4000
 SCALER_DISPSTAT0 = 0x101a4000
 ....
and in all cases, interesting bit is 0

may be i misguide you: i am trying to output CVBS (analogue PAL) signal but not HDMI
dom
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 8472
Joined: Wed Aug 17, 2011 7:41 pm

Re: drmModePageFlip with interlaced frame

Sat Sep 06, 2025 1:41 pm

max_verem wrote: ↑
Sat Sep 06, 2025 12:30 pm
 Many thanks for info, but bit27 of SCALER_DISPSTAT0 is always zero in my case (RPI4, PAL CVBS output, kernel 6.12.34+rpt-rpi-v8).
Ah - SCALER_DISPSTAT0 was correct for hdmi. Can you try SCALER_DISPSTAT1? (and if not then SCALER_DISPSTAT2).
max_verem
Posts: 6
Joined: Wed Sep 03, 2025 7:51 pm

Re: drmModePageFlip with interlaced frame

Sat Sep 06, 2025 2:18 pm

Thanks!

SCALER_DISPSTAT1 did a job for CVBS output.

It would be nice to get bit27 at frame argument of page_flip_handler but current approach works.
max_verem
Posts: 6
Joined: Wed Sep 03, 2025 7:51 pm

Re: drmModePageFlip with interlaced frame

Thu Sep 11, 2025 7:48 am

i did a tests on RPI5.

i am working with CVBS (analog PAL) output.

signal present but no glue how to get current output field information of CVBS output on RPI5.

hvs_regs of axi:gpu remains unchanged:

Code: Select all 

demo@dev-rpi5-1:~ $ cat /sys/kernel/debug/dri/axi:gpu/hvs_regs | grep _STATUS
SCALER6_FETCHER_STATUS = 0x00000000
 SCALER6_FETCH_STATUS = 0x00000000
 SCALER6_DISP0_STATUS = 0x00400000
 SCALER6_DISP1_STATUS = 0x00400000
 SCALER6_DISP2_STATUS = 0x00400000
 SCALER6_DL_STATUS = 0x00000000
i suspect it happens because on Pi5 the analogue video output is driven from RP1 and i use /dev/dri/by-path/platform-1f00144000.vec-card DRM device.

its debug sys directory:

Code: Select all 

demo@dev-rpi5-1:~ $ ls -als /sys/kernel/debug/dri/1f00144000.vec
total 0
0 drwxr-xr-x 5 root root 0 Sep 10 21:49 .
0 drwxr-xr-x 5 root root 0 Jun 26 17:58 ..
0 -r--r--r-- 1 root root 0 Sep 10 21:49 clients
0 drwxr-xr-x 2 root root 0 Sep 10 21:49 Composite-1
0 drwxr-xr-x 2 root root 0 Sep 10 21:49 crtc-0
0 drwxr-xr-x 2 root root 0 Sep 10 21:49 encoder-0
0 -r--r--r-- 1 root root 0 Sep 10 21:49 framebuffer
0 -r--r--r-- 1 root root 0 Sep 10 21:49 gem_names
0 -r--r--r-- 1 root root 0 Sep 10 21:49 internal_clients
0 -r--r--r-- 1 root root 0 Sep 10 21:49 name
0 -r--r--r-- 1 root root 0 Sep 10 21:49 state
does not contains any regs file.

any way to get current output field information of CVBS output on RPI5 ?

Code: Select all 

Linux dev-rpi5-1 6.12.45-v8-16k+ #1903 SMP PREEMPT Fri Sep 5 14:18:54 BST 2025 aarch64 GNU/Linux
njh
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 600
Joined: Wed Aug 09, 2017 2:07 pm

Re: drmModePageFlip with interlaced frame

Thu Sep 11, 2025 9:28 am

max_verem wrote: ↑
Thu Sep 11, 2025 7:48 am
 any way to get current output field information of CVBS output on RPI5 ?
No. With earlier kernels, the issue is moot: You always get top-then-bottom (25fps update).*

With very recent kernels (like the one you have), there's a flag inside the driver which flips about 32 lines into each field, but it's not user-visible.
If it was desperately needed and in the absence of any standard API for it, I suppose it could be exposed using debugfs...

*for PAL anyway. I suspect NTSC is the other way around, for more or less bogus reasons to do with line numbering conventions.
max_verem
Posts: 6
Joined: Wed Sep 03, 2025 7:51 pm

Re: drmModePageFlip with interlaced frame

Thu Sep 11, 2025 7:41 pm

would it correct to say that:

current kernel on RPI5 does not allow to field sync source interlaced framebuffers with CVBS (analogue video output) framebuffers ?
No. With earlier kernels, the issue is moot: You always get top-then-bottom (25fps update)
IMHO that is correct approach, you have either frame-based or field-based output/control.
njh
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 600
Joined: Wed Aug 09, 2017 2:07 pm

Re: drmModePageFlip with interlaced frame

Fri Sep 12, 2025 9:34 am

The timing of your post is a little unfortunate...

We've had multiple requests for Raspberry Pi 5 CVBS to support 50fps/60fps update (as it did on Pi 0-4). Arguably, the VBI event should be per-field, and we should allow but not mandate a page-flip for each one. And I only quite recently worked out how to implement this!

But I can see this is a problem when you need to scan out already-interlaced content. AFAIK nobody has raised this before.

Perhaps the best solution would be for us to try to make the sequence numbers behave consistently for fields, if possible. We'd need to figure out how those get from the driver to libdrm and see if we can fix them up when e.g. a mode change follows an odd number of fields. A module parameter is another option (to get back the old behaviour on RP1 VEC; I haven't looked at how feasible it would be for VC4).
6by9
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Re: drmModePageFlip with interlaced frame

Fri Sep 12, 2025 4:51 pm

njh wrote: ↑
Fri Sep 12, 2025 9:34 am
 But I can see this is a problem when you need to scan out already-interlaced content. AFAIK nobody has raised this before.
I don't believe DRM has ever supported being able to directly output an interlaced framebuffer to an interlaced display, and certainly not a line interleaved one as typically comes out of most codecs (certainly the Pi HW decoder gives line interleaved).
Doing so has many constraints (eg absolutely no scaling) that makes it too specialised. I guess a single field at a time could work, but requires extra work to generate it.

It doesn't help that most of the DRM devs generally don't care much for interlacing.
Software Engineer at Raspberry Pi Ltd. Views expressed are still personal views.
I'm not interested in doing contracts for bespoke functionality - please don't ask.
njh
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 600
Joined: Wed Aug 09, 2017 2:07 pm

Re: drmModePageFlip with interlaced frame

Mon Sep 15, 2025 9:21 am

Here's a potential workaround you could use. It's not great, but should work on any Raspberry Pi model for both HDMI and Composite:

Say you want to display interlaced frames Ab, Cd, Ef, Gh etc.

Then at field-rate, submit frame buffers containing Ab, Cb, Cd, Ed, Ef, Gf, Gh.

Depending on luck it will either display bCdEfGh or AbCdEfG (20ms delayed). Either way, it should be correctly interlaced.
max_verem
Posts: 6
Joined: Wed Sep 03, 2025 7:51 pm

Re: drmModePageFlip with interlaced frame

Mon Sep 15, 2025 6:43 pm

it is not a workaround but hack. similar hack was 20 years ago with SD video.

i actually started with specific test that in a case of initial phase (lucky case it related to first field) display either normal bars or horizontally flipped.

workaround is to produce 2 progressive frames from one interlaced frame. first have upper fields from origin and lower fields interpolated, but second frames has lower fields origin but upper fields interpolated.

but it better have a solution, at least to know which filed page_flip_handler belongs to. solution for RPI4 with registers works.
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