How to switch from HYP mode to SVC mode on Raspberry Pi 3 (AArch32)?
Hi,
I'm building my own RTOS from scratch for the Raspberry Pi 3 Model B (v1.2) in AArch32 mode.
My current focus is getting IRQ mode and ARM timer interrupts working.
Here is my setup:
→ This causes a crash.
If I comment out the msr cpsr_c, ... lines, the system proceeds to kernel_main, where I inspected the CPSR value and found it to be 0x6000015A.
From the mode bits (0b11010), I understand the CPU is in HYP mode.
I discovered that writing to CPSR using `msr cpsr_c, ...` doesn't work while in HYP mode.
This is unexpected, since I'm trying to boot into SVC mode in AArch32.
Here is my main question:
How can I safely exit HYP mode and switch to SVC mode early in the boot process?
(Adding kernel_old=1 seems to make things worse — it prevents even my LED/UART output from appearing. )
My goal is to set IRQ stacks using msr cpsr_c, ... and implement timer-based interrupts. But I need to escape HYP mode first. How should I do that?
Any help or clarification on how to properly enter SVC mode would be greatly appreciated.
Thanks in advance!
I'm building my own RTOS from scratch for the Raspberry Pi 3 Model B (v1.2) in AArch32 mode.
My current focus is getting IRQ mode and ARM timer interrupts working.
Here is my setup:
- I’m using AArch32 (not 64-bit).
- My `config.txt` is:
Code: Select all
arm_64bit=0
kernel=kernel7.img
enable_uart=1
device_tree=- LED control via GPIO and UART output is working correctly.
- All my source code is in a public Git repository. https://github.com/EI-77/rpi3-baremetal-rtos
- In `step1_UART/`, I implemented basic UART and GPIO drivers.
- In `step2_ARMTimet_IRQ/`, I’m working on ARM timer interrupt handling.
- The issue described in this post occurs in the `step2_ARMTimet_IRQ/` directory.
Code: Select all
// Switch to IRQ mode and set IRQ stack
mov r0, #0xD2 // CPSR: IRQ mode, FIQ/IRQ disabled
msr cpsr_c, r0
ldr sp, =__stack_top_irq
// Switch back to Supervisor (SVC) mode and reset SP
mov r0, #0xD3 // CPSR: SVC mode, FIQ/IRQ disabled
msr cpsr_c, r0
ldr sp, =__stack_topIf I comment out the msr cpsr_c, ... lines, the system proceeds to kernel_main, where I inspected the CPSR value and found it to be 0x6000015A.
From the mode bits (0b11010), I understand the CPU is in HYP mode.
I discovered that writing to CPSR using `msr cpsr_c, ...` doesn't work while in HYP mode.
This is unexpected, since I'm trying to boot into SVC mode in AArch32.
Here is my main question:
How can I safely exit HYP mode and switch to SVC mode early in the boot process?
(Adding kernel_old=1 seems to make things worse — it prevents even my LED/UART output from appearing. )
My goal is to set IRQ stacks using msr cpsr_c, ... and implement timer-based interrupts. But I need to escape HYP mode first. How should I do that?
Any help or clarification on how to properly enter SVC mode would be greatly appreciated.
Thanks in advance!
- cleverca22
- Posts: 9593
- Joined: Sat Aug 18, 2012 2:33 pm
Re: How to switch from HYP mode to SVC mode on Raspberry Pi 3 (AArch32)?
https://github.com/littlekernel/lk/comm ... c97031a21a
this is some changes i made to little-kernel ~5 years ago, to solve the same problem
this is some changes i made to little-kernel ~5 years ago, to solve the same problem
Re: How to switch from HYP mode to SVC mode on Raspberry Pi 3 (AArch32)?
Thank you very much! It worked perfectly — I really appreciate your help.
That was exactly what I needed! :D
That was exactly what I needed! :D
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