Verilog Links

Verilog Links

Jan-7-2025

Smart-DV Technologies

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Verilog Useful links

Verilog.net : Here you will find good collection of links on Verilog books, free simulators, Tutorials etc.
Rajesh Bawankule's Verilog Center : Good site to start with for Verilog beginners and also for engineers in this field.
Verilog HDL Author : Don Thomas Author of The Verilog Hardware Description Language
Alternate Verilog FAQ : Verilog FAQ

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Verification IP's

Smart Design Verification : This company develops SystemVerilog Verification IP for GigaBit Ethernet, 10G Ethernet, LIN Protocol, CAN, I2C, AMBA. Also provides design and verification services.
Wipro : This company provides complete ASIC design and verification soultions.
HCL : This company provides complete ASIC design and verification soultions.

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Syntax and semantics of Verilog (LRM)

IEEE Draft : Verilog simulation semantics from IEEE 1364 Draft document- DRAFT STANDARD VERILOG HDL)
Draft Semantice : Draft semantics for use in the VFE project.
ASICs the website : This website is basically the "ASIC....book". I started to learn Verilog first from this web page.
www.ee.ed.ac.uk : Verilog manual by Gerard.
Bucknell Verilog Manual : It's web manual, but there's a link to a pdf version for printing

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Verilog BFM Quick Reference

Commit : Comit Quick Reference Cards for Verilog
On-line Verilog quick reference guide : The best one for Verilog quick reference. This website also contains lot of other usefull information.
Verilog Quick reference Card : Another verilog quick reference from www.ece.uvic.ca.
Quick reference for Verilog : Another verilog quick reference from css.engineering.uiowa.edu.

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Verilog PLI

Hot PLI Stuff : Introduction to Verilog PLI and few examples
Project VeriPage : Your one stop source for Verilog Programming Language Interface (PLI) resources.

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Verilog Models

Verilog Models : Resistor and memory model
www.opencores.org : One stop for all source models you are looking.
Young Engineering : Has good list of simulation models for ADC, Serial EEPROM, A-Law, u-Law converters.

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Simulators

Verilog-XL : This is the most standard simulator in the market, as this is the sign off simulator.
NCVerilog : This is the compiled simulator which works as fast as VCS, and still maintains the sign off capabilities of Verilog-XL. This simulator is good when it comes to gate level simulations.
VCS : This is worlds fastest simulator, this is also a compiled simulator like NCverilog. This simulator is faster when it comes to RTL simulation. Few more things about this simulator are direct C kernel interface, Covermeter code coverage embedded, better integration with VERA and other Synopsys tools.
Finsim : This is 100% compatible simulator with Verilog-XL, runs on Linux, Windows and Solaris. This is compiled simulator like VCS and NCVerilog, but slower then VCS and NCVerilog. A 100ドル version is available, but I wonder what good this can do to Students ?
Modelsim : This is most popular simulator, It has got very good debugger, it supports SystemC, Verilog, VHDL and SystemVerilog.
Smash : mixed signal (spice), Verilog, VHDL simulator.
Silos : I don't know if anyone is using this, Use to be fast and stable.
Veritak : Verilog HDL Compiler/Simulator supporting major Verilog 2001 HDL features. It is integral environment including VHDL to Verilog translator, syntax highlight editor (Veripad), class hierarchy viewer ,multiple waveform viewer ,source analyzer,and more --available for Windows XP/2000. If you are looking for fast verilog HDL simulator with very good GUI for professional use, while keeping extremely inexpensive price , this is it. You can try Veritak for free for two weeks. This simulator costs around 50ドル.
MPSim : Axiom's MPSim is an integrated verification environment combining the fastest simulator in the industry with advanced testbench automation, assertion-based verification, debugging, and coverage analysis. Personally I have seen this simulator to be faster then NCsim, it comes with build in Vera support.

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Freeware Verilog Simulators

Veriwell : One of the best for students to start with, but bad luck that this one was brought by www.synapticad.com and latter introduced as Verilogger. There are currently Linux, Dos, Solaris and Windows version of Veriwell floating around the net, Supports up to 1000 Lines of code in freeware mode.
Icarus Verilog : Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. For synthesis, the compiler generates netlist in the desired format.
Cver : Cver is an interpreted Verilog simulator. It follows the 1995 IEEE P1364 standard LRM with some features from Verilog 2000 P1364 standard. Although, because it is used in large company design flows, various changes from the P1364 standard have been made to match results of other simulators. It implements full PLI including PLI vpi_ application programming interface (API) as defined by Verilog 2000 LRM. It has a GDB style command line debugger that implements normal OVI statement level debugger plus GDB ease of use enhancements.
Verilator : Verilator is a compiled cycle-based simulator, which is free, but performs as fast as the commercial products.

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VCD Viewer

nWave : One of the best VCD viewer, with support for large VCD dumps.
Undertow : Undertow waveform viewer.
GTKWave : Freeware VCD viewer, Seems far better then other free VCD viewers.
Dinotrace : Freeware VCD viewer from veritools

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Freeware VCD Viewers

DinoTrace : Tried just once, had very difficult time controlling the color of waveform, seems to be ok for Linux env.
GTKWave : Best VCD viewer available in net, Hum seems to crash for large VCD files, works on Windows.

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Student Version Synthesis Tools

Altera's E+Max : Free tool, synthesis and place&route tool for CPLD and FPGA.
Xilinx Web Edition : Free tool for Verilog synthesis and Place and Route of Xilinx CPLD and FPGA

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EDA Industry Working Groups

Open Verilog International (OVI) :
Verilog Synthesis Subset Working Group (IEEE PAR 1364.1) :
Verilog Analog Mixed Signal (Verilog-ams) Working Group :
Standard Delay Format (SDF) Study Group (IEEE PAR 1497) :
Advanced Library Format (alf) Working Group :
Verilog Formal Verification (vfv) Working Group :

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Verilog Multimedia Tutorials

Verilog tutorial : A very good multimedia tutorial from Aldec

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Code Coverage

Verification Navigator : An integrated design verification environment that enables a consistent, easy-to-use and efficient verification methodology with a powerful set of best-in-class tools for managing the HDL verification process. These tools include HDL checking, coverage analysis, test suite analysis and FSM analysis. The environment includes an extensible flow manager for easy incorporation of custom verification flows. Verification Navigator supports Verilog, VHDL and mixed language designs and integrates seamlessly with all leading simulation environments.
SureCov : Engineering teams designing today's chips and semiconductor IP cores need to know, with confidence, how thoroughly the functional test suite is exercising the design. Verisity's SureCov measures FSM and code coverage with the lowest simulation overhead of any tool available, and without requiring changes to the source design. The SureSight graphical user interface shows exactly which parts of the design have been covered and which have not.
Code Coverage Tool : A freeware code coverage tool. Code coverage tool is a Verilog code coverage analysis tool that can be useful for determining how well a test suite is covering the design under test.

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Linting

Leda : Leda is a code purification tool for designers using the Verilogョ and VHDL Hardware Description Language (HDL). Leda is uniquely qualified to analyze HDL code pre-synthesis and pre-simulation and is totally compatible with all popular synthesis and simulation tools and flows. By automating more than 500 design checks for language syntax, semantics and questionable synthesis/simulation constructs, Leda detects common as well as subtle and hard-to-find code defects, thus freeing designers to focus on the art of design.
HDLint : A power full linting tool for VHDL and Verilog.
nLint : nLint is a comprehensive HDL design rule checker fully integrated with the Debussy debugging system.
SureLint : Designers need tools to analyze and debug their designs before integrating with the rest of the project. SureLint offers finite state machine (FSM) analysis, race detection, and many additional checks the most complete lint tool on the market.

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Verilog Verification with PLI

Jove : The Open Verification Environment for the Java (TM) Platform. Jove is a set of Java APIs and tools to enable Verilog hardware design verification of ASICs and FPGAs using the Java programming language. Jove has been tested extensively with Synopsys VCS and to a lesser extent with the GPL version of cver by Pragmatic C Software.
Ruby-VPI : Ruby-VPI is a Ruby interface to Verilog VPI. It lets you create complex Verilog test benches easily and wholly in Ruby.
MyHdl : MyHDL is a Python package for using Python as a hardware description and verification language.
VTracer project : VTracer is a set of tools (subprojects) used for Verilog Testbench development.
Verilog-Pli : Verilog
TestBuilder : TestBuilder is an open source initiative providing functional verification tools to hardware developers and incorporating the massive peer review capabilities that only freely distributed open source software allows.
Teal : open source c++ class library for verification

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Utils

FSMDesigner : FSMDesigner is a Java-based Finite State Machine (FSM) editor, which allows the hardware designer to specify complex control circuits in an easy and comfortable way. The graphical FSM is converted into a proprietary state/flow-table format called fsm2. It can be translated into efficient and synthesizable Verilog HDL code by a compiler called fsm2v designed at our chair. FSMDesigner is based on the Simple-Moore FSM model, which completely eliminates the output function by using parts of the state vector as outputs.
TimeGen : TimeGen is an engineering CAD tool which allows a digital design engineer the capability to quickly and effectively draw digital timing diagrams. The waveforms can easily be exported to other Window programs, such as Microsoft Word, for use in writing design specifications. TimeGen is less price compared to other tools.
Waveformer : Tool for drawing waveforms, to be used for documentation purpose.
Perlilog : Perlilog is a design tool, whose main target is easy integration of Verilog IP cores for System-on-Chip (SoC) designs. The philosophy behind Perilog is that an IP core should be like a black box. Fitting it for a certain purpose should be as easy as defining the desired requirements. Connecting the cores, to become a system, should be as easy as drawing a block diagram. Perlilog is written in Perl, currently with no GUI. While the scripts, that the system consists of, are rather sophisticated, only plain Perl knowledge is needed to use its scripting capabilities.
Timing Tool : TimingTool is a free to use on-line Timing Diagram Editor. This tool provides very good VHDL and Verilog test benches and requires no download or installation.

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Miscellaneous

verilog2vhdl : Verilog to VHDL translation
John Cooley Site for ASIC Tools : Website to start with if you want to get feedback on any eda tool in market, also lot of users share there experience.
Converter from Verilog to html : A free perl script that converts Verilog to html with most things linked. Also creates hierarchies and indexes for your design.
International Cadence User group : Conference archives, a special interest group and FAQ.
OPEN MODEL FORUM (P1499) : Open Model Forum (P1499) Home Page
Verilog 2000, What's new : News features in Verilog 2000-2001 discussed
Verilog mode for emacs and Xemacs : Verilog Mode for famous Emacs editor.
hdlmaker : Generating top-level netlist from lower-level blocks. Nice program to make the top level files from the lower modules. Saves lot of time.
mktree : Creating module connection files
Verilog HDL Obfuscator : As the name suggests, make the Verilog code unreadable, but functionally correct.
Source Navigator : Source Navigator for Verilog is full featured tool for editing and navigating through large projects with many Verilog files. It parses Verilog code into a database that can be used to navigate files, trace connectivity, and find modules and signals in the design.
Perl/Python/Tcl Interface to VPI : This page is dedicated to linking scripting languages such as Perl,Python and Tcl to any freely available EDA tools.
Free timing diagram editor : Browser based timing diagram editor, Hum looks really cool
Peter Chambers "10 commandments of excellent design" : This paper talks about common things that a design should know about.
Public domain Verilog resources : This site contains links to public domain, shareware, or other no-charge-for-use design resources
ASIC, EDA, Software and High Level Syntheis : This website is of a ASIC Front End Designer, which is site on ASIC, EDA, Software and High Level Syntheis along with some misc stuff.
VLSI Chip Design : This website contains ASIC synthesis information.

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Do you have any Comment? mail me at:deepak@asic-world.com