CM-1

Now to descibe a different "one Bit" concept:

Each one of the two Logic Units basically is a 74151 like 8:1 multiplexer.
The select inputs A,B are read from data memory, while C is read from the Flags
(Carry Flag, for instance.)
Data inputs for the multiplexers are not shown in the block diagram,
but you sure can imagine from our previous examples how to set them
for configurating our Logic Units.

For instance: when building a full adder, Q is a three_input XOR,
so we set the data inputs of the Q multiplexer to 10010110.
Our carry output F to the Flags is active, when two or more
of the inputs A, B, C are 1.
So we set the F multiplexer inputs to 11101000.

A complete list for configurating the Logic Units would be very long:
2 * 8 = 16 Bit, that's 65536 possible combinations.

Note, that the Flag "section" is different from the usual
microprocessor architecture.
It consists of two parts:
A "scratch pad" area of non_dedicated Flags, means that there
isn't a definition which Flag becomes N, Z and so on...
it entirely depends on the software, which uses the Flags.
And a set of I/O pins, to communicate with the "outerworld"
(other Bit serial processors or peripherals, for instance),
or maybe for conditional instruction execution.

The instruction word for such a design tends to be rather large,
especially when building a three operand machine, that could be able
to read one Flag, and to write the result into another.
Maybe there is only one sequencer, that contains the program counter,
fetches the instructions from program memory, and applys them to all
of the processors in parallel... and a processor only can choose
to execute or to skip/discard the instruction.

Nevertheless, you may want to change/modify the design when trying
to wire three such processors together to calculate a CORDIC algorithm.

To keep code size small, it might be a good idea to integrate a
"repeat count" into each instruction word since we are going for
chunks of eight or more Bits in data memory.
But we would need three counters for generating the memory
read/write address then.

Another question is, what to do with the first Bit when repeating
an instruction several times, because we might want to have the Carry
that goes into the first Bit set to 0 or 1 sometimes.

"What's the practical use of that thing ?",
you may ask.

The Connection Machine (CM-1 or CM-2) had 65536 one Bit processors,
each one had an ALU which was based on a (more or less) similar concept.

Applications circled around artificial intelligence, data encryption,
image processing and such...

...But enough about computer science. Now for the practical use:
If you happen to be an evil genius, out to build your own giant metal tarantula,
which is moved by todays stepper motors (instead of steam powered stuff),
you might want to calculate linear ramps for 64 motors with 64 Bit
fixed point math. And the question is: what implementation would be more difficult ?
Building a 64 Bit high speed ALU, which has a complicated carry mechanism,
or 64 Bit serial processors running in parallel, controlled by a not_so_usual
sequencer ?

Decisions, decisions...

If you have success, please tell us what country you live in...
so we could have a chance to be as far away as possible.

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